prcctrl.vhd

这个是国外大学的项目代码

------------------------------------------------------------------------
--  prcctrl.vhd -- Process read control
------------------------------------------------------------------------
--  Author : Kovacs Laszlo - Attila 
------------------------------------------------------------------------
-- Software version: Xilinx ISE 7.1.04i
--                   WebPack
------------------------------------------------------------------------
-- This module reads the image process.
-- It generates the 4 least significant bits of the address to read 
-- the process. And stores in registers the source and the destination 
-- image number and the convolution kernel.
------------------------------------------------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity prcctrl is
    Port ( CLK      : in std_logic;
           EN       : in std_logic;
           DONE     : out std_logic;
           DI       : in std_logic_vector(7 downto 0);
           ADR      : out std_logic_vector(3 downto 0);
           IMGSRC   : out std_logic_vector(3 downto 0);
           IMGDEST  : out std_logic_vector(3 downto 0);
           MASK0    : out std_logic_vector(7 downto 0);
           MASK1    : out std_logic_vector(7 downto 0);
           MASK2    : out std_logic_vector(7 downto 0);
           MASK3    : out std_logic_vector(7 downto 0);
           MASK4    : out std_logic_vector(7 downto 0);
           MASK5    : out std_logic_vector(7 downto 0);
           MASK6    : out std_logic_vector(7 downto 0);
           MASK7    : out std_logic_vector(7 downto 0);
           MASK8    : out std_logic_vector(7 downto 0);
           MASK9    : out std_logic_vector(7 downto 0));
end prcctrl;

architecture Behavioral of prcctrl is

signal iADR : std_logic_vector(3 downto 0) := "0000";
signal iIMGSRC, iIMGDEST : std_logic_vector(3 downto 0) := "0000";
signal iMASK0,iMASK1,iMASK2,iMASK3,iMASK4,iMASK5,iMASK6,iMASK7,iMASK8,
    iMASK9 : std_logic_vector(7 downto 0) := "00000000" ;

begin
    
    DONE <= '1' when iADR = "1110" else '0';
    ADR <= iADR;
    IMGSRC <= iIMGSRC;
    IMGDEST <= iIMGDEST;
    MASK0 <= iMASK0;
    MASK1 <= iMASK1;
    MASK2 <= iMASK2;
    MASK3 <= iMASK3;
    MASK4 <= iMASK4;
    MASK5 <= iMASK5;
    MASK6 <= iMASK6;
    MASK7 <= iMASK7;
    MASK8 <= iMASK8;
    MASK9 <= iMASK9;


    process(CLK)
    begin    
        if rising_edge(CLK) then
            if EN = '0' then
                iADR <= "0000";
            elsif not (iADR = "1110") then
                iADR <= iADR + 1;
            end if;
        end if;
    end process;
    
    process(CLK)
    begin    
        if rising_edge(CLK) then
            case iADR is
                when "0010" =>
                    iIMGSRC <= DI(3 downto 0);
                when "0011" =>
                    iIMGDEST <= DI(3 downto 0);
                when "0100" =>
                    iMASK0 <= DI;
                when "0101" =>
                    iMASK1 <= DI;
                when "0110" =>
                    iMASK2 <= DI;
                when "0111" =>
                    iMASK3 <= DI;
                when "1000" =>
                    iMASK4 <= DI;
                when "1001" =>
                    iMASK5 <= DI;
                when "1010" =>
                    iMASK6 <= DI;
                when "1011" =>
                    iMASK7 <= DI;
                when "1100" =>
                    iMASK8 <= DI;
                when "1101" =>
                    iMASK9 <= DI;
                when others =>
            end case;
        end if;
    end process;
end Behavioral;