sram.vhd

这个是国外大学的项目代码

------------------------------------------------------------------------
--  sram.vhd -- Synchronous SRAM interface
------------------------------------------------------------------------
--  Author : Kovacs Laszlo - Attila 
------------------------------------------------------------------------
-- Software version: Xilinx ISE 7.1.04i
--                   WebPack
------------------------------------------------------------------------
-- The sram is the synchronous interface for the asynchronous SRAM. 
-- It gives access to the memory after the following priority: 
-- epp (Epp controller), 
-- ctrl (global control), 
-- prc2 (processing unit), 
-- imgctrl (image header reading module) and 
-- img (image display). 
------------------------------------------------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity sram is
    Port ( CLK     : in std_logic;
           --sram
           RAMDB   : inout std_logic_vector(7 downto 0);
           RAMADR  : out std_logic_vector(18 downto 0);
           RAMCS0  : out std_logic;
           RAMCS1  : out std_logic;
           RAMOE   : out std_logic;
           RAMWR   : out std_logic;
           --general
           SDO     : out std_logic_vector(7 downto 0);
           --eppctrl
           EDO     : in std_logic_vector(7 downto 0);
           EADR    : in std_logic_vector(19 downto 0);
           EOE     : in std_logic;
           EWR     : in std_logic;
           EBUSY   : in std_logic;
           --ctrl
           CRD     : in std_logic;
           CADR    : in std_logic_vector(19 downto 0);
           --imgctrl
           ICRD    : in std_logic;
           ICADR   : in std_logic_vector(19 downto 0);
           --display
           IADR    : in std_logic_vector(19 downto 0);
           --prc
           PBUSY   : in std_logic;
           PRD     : in std_logic;
           PWR     : in std_logic;
           PDO     : in std_logic_vector(7 downto 0);
           PADR    : in std_logic_vector(19 downto 0));
end sram;
architecture Behavioral of sram is

begin

    process(CLK)
    begin
        if rising_edge(CLK) then
            RAMDB  <= "ZZZZZZZZ";
            RAMCS0 <= '1';
            RAMCS1 <= '1';
            RAMOE  <= '1';
            RAMWR  <= '1';
            SDO <= RAMDB;
            if EBUSY = '1' then
                RAMADR <= EADR(18 downto 0);
                RAMCS0 <= EADR(19);
                RAMCS1 <= not EADR(19);
                RAMOE <= EOE;
                RAMWR <= EWR;
                if EWR = '0' then
                    RAMDB <= EDO;
                end if;
            elsif CRD = '1' then
                RAMADR <= CADR(18 downto 0);
                RAMCS0 <= CADR(19);
                RAMCS1 <= not CADR(19);
                RAMOE <= '0';
                RAMWR <= '1';
            elsif PBUSY = '1' then 
                RAMADR <= PADR(18 downto 0);
                RAMCS0 <= PADR(19);
                RAMCS1 <= not PADR(19);
                RAMOE <= not PRD;
                RAMWR <= not PWR;
                if PWR = '1' then
                    RAMDB <= PDO;
                end if;
            elsif ICRD = '1' then
                RAMADR <= ICADR(18 downto 0);
                RAMCS0 <= ICADR(19);
                RAMCS1 <= not ICADR(19);
                RAMOE <= '0';
                RAMWR <= '1';
            else
                RAMADR <= IADR(18 downto 0);
                RAMCS0 <= IADR(19);
                RAMCS1 <= not IADR(19);
                RAMOE <= '0';
                RAMWR <= '1';
            end if;
        end if;
    end process;

end Behavioral;