cadd.vhd

来自「这个是国外大学的项目代码」· VHDL 代码 · 共 43 行

------------------------------------------------------------------------
--  cadd.vhd -- Adder
------------------------------------------------------------------------
--  Author : Kovacs Laszlo - Attila 
------------------------------------------------------------------------
-- Software version: Xilinx ISE 7.1.04i
--                   WebPack
------------------------------------------------------------------------
-- 16bit adder
------------------------------------------------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity cadd is
    Port ( CLK  : in std_logic;
           EN   : in std_logic;
           DI0  : in std_logic_vector(15 downto 0);
           DI1  : in std_logic_vector(15 downto 0);
           DO   : out std_logic_vector(15 downto 0));
end cadd;
architecture Behavioral of cadd is

signal res : std_logic_vector(15 downto 0) := "0000000000000000";
signal iDO : std_logic_vector(15 downto 0) := "0000000000000000";

begin

    DO <= iDO;

    process(CLK)
    begin
        if rising_edge(CLK) and EN = '1' then
            iDO <= res;
        end if;
    end process;
    
    res <= DI0 + DI1;

end Behavioral;