sram.hmm.txt

这个是国外大学的项目代码

------------------------------------------------------------------------
--  sram.vhd -- Synchronous SRAM interface
------------------------------------------------------------------------
--  Author : Kovacs Laszlo - Attila 
------------------------------------------------------------------------
-- Software version: Xilinx ISE 7.1.04i
--                   WebPack
------------------------------------------------------------------------
-- The sram is the synchronous interface for the asynchronous SRAM. 
-- It gives access to the memory after the following priority: 
-- epp (Epp controller), 
-- ctrl (global control), 
-- prc2 (processing unit), 
-- imgctrl (image header reading module) and 
-- img (image display). 
------------------------------------------------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity sram is
    Port ( CLK     : in std_logic;
           --sram
           RAMDB   : inout std_logic_vector(7 downto 0);
           RAMADR  : out std_logic_vector(18 downto 0);
           RAMCS0  : out std_logic;
           RAMCS1  : out std_logic;
           RAMOE   : out std_logic;
           RAMWR   : out std_logic;
           --general
           SDO     : out std_logic_vector(7 downto 0);
           --eppctrl
           EDO     : in std_logic_vector(7 downto 0);
           EADR    : in std_logic_vector(19 downto 0);
           EOE     : in std_logic;
           EWR     : in std_logic;
           EBUSY   : in std_logic;
           --ctrl
           CRD     : in std_logic;
           CADR    : in std_logic_vector(19 downto 0);
           --imgctrl
           ICRD    : in std_logic;
           ICADR   : in std_logic_vector(19 downto 0);
           --display
           IADR    : in std_logic_vector(19 downto 0);
           --prc
           PBUSY   : in std_logic;
           PRD     : in std_logic;
           PWR     : in std_logic;
           PDO     : in std_logic_vector(7 downto 0);
           PADR    : in std_logic_vector(19 downto 0));
end sram;

architecture Behavioral of sram is

signal inADR : std_logic_vector(19 downto 0) := "00000000000000000000";
signal iDATA : std_logic_vector(7 downto 0) := "00000000";
signal iWR, iRD : std_logic := '0';
begin
    
    inADR <= EADR when EBUSY = '1' else
            PADR when PBUSY = '1' else
            CADR when CRD = '1' else
            ICADR when ICRD = '1' else
            IADR;

    iDATA <= EDO when EBUSY = '1' else
             PDO;

    iWR <= '1' when EWR = '0' or PWR = '1' else '0';
    
    process(CLK)
    begin
        if rising_edge(CLK) then
            RAMCS0 <= inADR(19);
            RAMCS1 <= not inADR(19);
            RAMADR <= inADR(18 downto 0);
            RAMOE  <= iWR;
            RAMWR  <= not iWR;
            SDO <= RAMDB;
            if iWR = '1' then
                RAMDB  <= iDATA;
            else
                RAMDB <= (others => 'Z');
            end if;
        end if;
    end process;

end Behavioral;