imgrgb24.vhd

这个是国外大学的项目代码

------------------------------------------------------------------------
--  img.vhd -- RGB Image reading module
------------------------------------------------------------------------
--  Author : Kovacs Laszlo - Attila 
------------------------------------------------------------------------
-- Software version: Xilinx ISE 7.1.04i
--                   WebPack
------------------------------------------------------------------------
-- 3 bytes 8:8:8 (RGB) bits
-- This reads the image from the memory, in synchron with the vga signal 
-- generator, forwards to the PWM control unit and gives the signals for 
-- the vga port. 
------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;


entity imgrgb24 is
    Port ( CLK   : in std_logic;
           DSPEN : out std_logic;
           --vga 
           VGAHC  : in std_logic_vector(10 downto 0);
           VGAVC  : in std_logic_vector(9 downto 0);
           --pixel data
           DRED  : out std_logic_vector(7 downto 0);
           DGRN  : out std_logic_vector(7 downto 0);
           DBLU  : out std_logic_vector(7 downto 0);
           --data 
           IDI  : in std_logic_vector(7 downto 0);
           IADR : out std_logic_vector(19 downto 0);
           --imgctrl
           SADR : in std_logic_vector(19 downto 0);
           IMGW : in std_logic_vector(10 downto 0);
           IMGH : in std_logic_vector(10 downto 0));
end imgrgb24;

architecture Behavioral of imgrgb24 is

--odd and even addresses
signal oadr, eadr : std_logic_vector(19 downto 0) 
    := "00000000000000000000";
--horizntal and vertical in image bounds flags
signal hin, vin : std_logic := '0';
--odd and even data registers
signal ored, ogrn, oblu, ered, egrn, eblu  
    : std_logic_vector(7 downto 0) := "00000000";
signal colorcnt : std_logic_vector(2 downto 0) := "000";
--horizontal display bounds
signal hinc : std_logic_vector(7 downto 0) := "00000000";

begin

    hin <= '1' when VGAHC(10 downto 2) < IMGW(8 downto 0) and 
                            IMGW < "00101000001" else '0';
    vin <= '1' when VGAVC(9 downto 1) < IMGH(8 downto 0) and 
                            IMGH < "00011110001" else '0';

    colorcnt <= VGAHC(2 downto 0);

    DSPEN <= '1' when vin = '1' and hinc(0) = '1' else '0';

    process(CLK)
    begin
        if rising_edge(CLK) then
            hinc <= hin & hinc(7 downto 1);
        end if;
    end process;

    process(CLK)
    begin
        if rising_edge(CLK) then
            if colorcnt = "110" then
                dred <= ored;
                dgrn <= ogrn;
                dblu <= oblu;
            elsif colorcnt = "010" then
                dred <= ered;
                dgrn <= egrn;
                dblu <= eblu;
            end if;
        end if;
    end process;

    --address counters
    process(CLK)
    begin
        if rising_edge(CLK) then
            if hin = '0' and vin = '0' then
                oadr <= SADR;
                eadr <= SADR;
            elsif hin = '1' and vin = '1' and 
                colorcnt(1 downto 0) /= "11" then
                if VGAVC(0) = '0' then
                    oadr <= oadr + 1;
                    IADR <= oadr;
                else
                    eadr <= eadr + 1;
                    IADR <= eadr;
                end if;
            end if;
        end if;
    end process;

    --fill the odd and even registers with data
    process(CLK)
    begin 
        if rising_edge(CLK) then
            case colorcnt is
            when "011" =>
                ored <= IDI;
            when "100" =>
                ogrn <= IDI;
            when "101" =>
                oblu <= IDI;
            when "111" =>
                ered <= IDI;
            when "000" =>
                egrn <= IDI;
            when "001" =>
                eblu <= IDI;
            when others =>
            end case;
        end if;
    end process;

end Behavioral;