vga.vhd

这个是国外大学的项目代码

------------------------------------------------------------------------
--  vga.vhd -- VGA signal generator 
------------------------------------------------------------------------
--  Author : Kovacs Laszlo - Attila 
------------------------------------------------------------------------
-- Software version: Xilinx ISE 7.1.04i
--                   WebPack
------------------------------------------------------------------------
-- VGA signal generator with an initial 2.5 seconds off signal 
-- needed for some old CRT monitors. 
------------------------------------------------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity vga is
    Port ( CLK    : in std_logic;
           VGAHS  : out std_logic;
           VGAVS  : out std_logic;
           VGADSP : out std_logic;
           VGAHC  : out std_logic_vector(10 downto 0);
           VGAVC  : out std_logic_vector(9 downto 0);
           HDELAY  : in std_logic_vector(2 downto 0);
           VDELAY  : in std_logic_vector(3 downto 0));
end vga;

architecture Behavioral of vga is
--hdisplay end 640
constant hdispe : std_logic_vector(10 downto 0) :=  "10100000000";
--hsync start                                       
constant hsyncs : std_logic_vector(10 downto 0) :=  "10101000010";
--hsync end 
constant hsynce : std_logic_vector(10 downto 0) :=  "10110110000";
--hcount end 31469Hz ~= 1591 = 11000110111 clk ~ 1600 clk
constant hcounte : std_logic_vector(10 downto 0) := "11000111111";
--vdisplay end 480
constant vdispe : std_logic_vector(9 downto 0) :=  "0111100000"; 
--vsync start 
constant vsyncs : std_logic_vector(9 downto 0) :=  "0111110101"; 
--vsync end 
constant vsynce : std_logic_vector(9 downto 0) :=  "0111110111"; 
--vcount end 59.94Hz ~= 521 = 1000001001 lines ~ 528
constant vcounte : std_logic_vector(9 downto 0) := "1000001111"; 
--horizontal and vertical counter
signal ihc     : std_logic_vector(10 downto 0) := hsyncs;
signal ivc     : std_logic_vector(9 downto 0) := vsyncs;
--initial off signal counter 
--needed for some old crt monitors
signal envga : std_logic := '0';                
signal initvga : std_logic_vector(27 downto 0) 
    := "0000000000000000000000000000";
--horizontal counter limit
signal hcount, hcount0 : std_logic_vector(10 downto 0) := "00000000000";

begin

    VGAHS <= '0' when ihc >= hsyncs and ihc < hsynce else '1';
    VGAVS <= '0' when ivc >= vsyncs and ivc < vsynce else '1';
    VGADSP <= '1' when ihc < hdispe and ivc < vdispe else '0';
    VGAHC <= ihc;
    VGAVC <= ivc;
    
    hcount0 <= hcounte - HDELAY;
    hcount <= hcount0 - VDELAY when ivc = vsyncs else hcount0;
    
    envga <= initvga(27);

    --initial suspend delay
    process(CLK)
    begin
        if rising_edge(CLK) then
            if envga = '0' then
                initvga <= initvga + 1;
            end if;
        end if;
    end process;

    --horizontal counter
    process(CLK)
    begin
        if rising_edge(CLK) then
            if envga = '1' then
                if ihc = hcount then
                    ihc <= "00000000000";        
                else
                    ihc <= ihc + 1;
                end if;
            end if;
        end if;
    end process;

    --vertical counter
    process(CLK)
    begin
        if rising_edge(CLK) then
            if ihc = hcount and envga = '1' then
                if ivc = vcounte then
                    ivc <= "0000000000";
                else
                    ivc <= ivc + 1;
                end if;
            end if;
        end if;
    end process;

end Behavioral;