cmul.vhd

来自「这个是国外大学的项目代码」· VHDL 代码 · 共 53 行

------------------------------------------------------------------------
--  cmul.vhd -- Multiplier
------------------------------------------------------------------------
--  Author : Kovacs Laszlo - Attila 
------------------------------------------------------------------------
-- Software version: Xilinx ISE 7.1.04i
--                   WebPack
------------------------------------------------------------------------
-- This module performs left shift according to the least significant 
-- 3bits of the MASK. If the most significant bit of MASK is '1' than
-- it is calculated the two's complement of the previous result ('res').
------------------------------------------------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity cmul is
    Port ( CLK  : in std_logic;
           EN   : in std_logic;
           MASK : in std_logic_vector(3 downto 0);
           DI   : in std_logic_vector(7 downto 0);
           DO   : out std_logic_vector(15 downto 0));
end cmul;
architecture Behavioral of cmul is

signal res : std_logic_vector(12 downto 0) := "0000000000000";
signal iDO  : std_logic_vector(15 downto 0) := "0000000000000000";

begin

    DO <= iDO;
    
    process(CLK)
    begin
        if rising_edge(CLK) and EN = '1' then
            iDO <= "000"&res;
        end if;
    end process;

    with MASK(2 downto 0) select
    res <= "0000000000000" when "000",
           "00000"&DI      when "001",
           "0000"&DI&'0'   when "010",
           "000"&DI&"00"   when "011",
           "00"&DI&"000"   when "100",
           '0'&DI&"0000"   when "101",
           DI&"00000"      when others;
    

end Behavioral;