pixel.vhd

这个是国外大学的项目代码

------------------------------------------------------------------------
--  pixel.vhd -- PWM select
------------------------------------------------------------------------
--  Author : Kovacs Laszlo - Attila 
------------------------------------------------------------------------
-- Software version: Xilinx ISE 7.1.04i
--                   WebPack
------------------------------------------------------------------------
-- The pixel is a multiplexer which selects one of the 8 pulse width 
-- modulators.
------------------------------------------------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity pixel is
    Port ( CLK   : in std_logic;
           CLK2X : in std_logic;
           CLK2  : in std_logic;
           CLK4  : in std_logic;
           CLK8  : in std_logic;
           RED   : out std_logic;
           GRN   : out std_logic;
           BLU   : out std_logic;
           DRED  : in std_logic_vector(7 downto 0);
           DGRN  : in std_logic_vector(7 downto 0);
           DBLU  : in std_logic_vector(7 downto 0);
           PWMNR : in std_logic_vector(2 downto 0));
end pixel;

architecture Behavioral of pixel is

component pwmmd is
    Port ( CLK2X : in std_logic;
           CLK   : in std_logic;
           CLK2  : in std_logic;
           CLK4  : in std_logic;
           DO    : out std_logic;
           DI    : in std_logic_vector(7 downto 0));
end component;

component pwmeq is
    Port ( CLK2X : in std_logic;
           CLK   : in std_logic;
           CLK2  : in std_logic;
           CLK4  : in std_logic;
           DO    : out std_logic;
           DI    : in std_logic_vector(7 downto 0));
end component;

component pwmhi is
    Port ( CLK2X : in std_logic;
           CLK   : in std_logic;
           CLK2  : in std_logic;
           CLK4  : in std_logic;
           DO    : out std_logic;
           DI    : in std_logic_vector(7 downto 0));
end component;

component pwmlo is
    Port ( CLK2X : in std_logic;
           CLK   : in std_logic;
           CLK2  : in std_logic;
           CLK4  : in std_logic;
           DO    : out std_logic;
           DI    : in std_logic_vector(7 downto 0));
end component;

component pwm18 is
    Port ( CLK2X : in std_logic;
           CLK   : in std_logic;
           CLK2  : in std_logic;
           CLK4  : in std_logic;
           CLK8  : in std_logic;
           DO    : out std_logic;
           DI    : in std_logic_vector(7 downto 0));
end component;

component pwm2x is
    Port ( CLK2X : in std_logic;
           CLK   : in std_logic;
           CLK2  : in std_logic;
           CLK4  : in std_logic;
           CLK8  : in std_logic;
           DO    : out std_logic;
           DI    : in std_logic_vector(7 downto 0));
end component;

component pwminv2x is
    Port ( CLK2X : in std_logic;
           CLK   : in std_logic;
           CLK2  : in std_logic;
           CLK4  : in std_logic;
           CLK8  : in std_logic;
           DO    : out std_logic;
           DI    : in std_logic_vector(7 downto 0));
end component;

component pwm2xeq is
    Port ( CLK2X : in std_logic;
           CLK   : in std_logic;
           CLK2  : in std_logic;
           CLK4  : in std_logic;
           DO    : out std_logic;
           DI    : in std_logic_vector(7 downto 0));
end component;


signal rmd, gmd, bmd, req, geq, beq, rhi, ghi, bhi, rlo, glo, blo, 
       r2x, g2x, b2x, rinv2x, ginv2x, binv2x,
       rmd2x, gmd2x, bmd2x, req2x, geq2x, beq2x : std_logic := '0';

begin

    pwmmdred : pwmmd port map(CLK2X, CLK, CLK2, CLK4, rmd, DRED);
    pwmmdgrn : pwmmd port map(CLK2X, CLK, CLK2, CLK4, gmd, DGRN);
    pwmmdblu : pwmmd port map(CLK2X, CLK, CLK2, CLK4, bmd, DBLU);
                                                 
    pwmeqred : pwmeq port map(CLK2X, CLK, CLK2, CLK4, req, DRED);
    pwmeqgrn : pwmeq port map(CLK2X, CLK, CLK2, CLK4, geq, DGRN);
    pwmeqblu : pwmeq port map(CLK2X, CLK, CLK2, CLK4, beq, DBLU);

    pwmhired : pwmhi port map(CLK2X, CLK, CLK2, CLK4, rhi, DRED);
    pwmhigrn : pwmhi port map(CLK2X, CLK, CLK2, CLK4, ghi, DGRN);
    pwmhiblu : pwmhi port map(CLK2X, CLK, CLK2, CLK4, bhi, DBLU);

    pwmlored : pwmlo port map(CLK2X, CLK, CLK2, CLK4, rlo, DRED);
    pwmlogrn : pwmlo port map(CLK2X, CLK, CLK2, CLK4, glo, DGRN);
    pwmloblu : pwmlo port map(CLK2X, CLK, CLK2, CLK4, blo, DBLU);

    pwmmd2xred : pwm18 port map(
        CLK2X, CLK, CLK2, CLK4, CLK8, rmd2x, DRED);
    pwmmd2xgrn : pwm18 port map(
        CLK2X, CLK, CLK2, CLK4, CLK8, gmd2x, DGRN);
    pwmmd2xblu : pwm18 port map(
        CLK2X, CLK, CLK2, CLK4, CLK8, bmd2x, DBLU);
                                                 
    pwm2xred : pwm2x port map(CLK2X, CLK, CLK2, CLK4, CLK8, r2x, DRED);
    pwm2xgrn : pwm2x port map(CLK2X, CLK, CLK2, CLK4, CLK8, g2x, DGRN);
    pwm2xblu : pwm2x port map(CLK2X, CLK, CLK2, CLK4, CLK8, b2x, DBLU);

    pwm2red : pwminv2x port map(
        CLK2X, CLK, CLK2, CLK4, CLK8, rinv2x, DRED);
    pwm2grn : pwminv2x port map(
        CLK2X, CLK, CLK2, CLK4, CLK8, ginv2x, DGRN);
    pwm2blu : pwminv2x port map(
        CLK2X, CLK, CLK2, CLK4, CLK8, binv2x, DBLU);

    pwmeq2xred : pwm2xeq port map(CLK2X, CLK, CLK2, CLK4, req2x, DRED);
    pwmeq2xgrn : pwm2xeq port map(CLK2X, CLK, CLK2, CLK4, geq2x, DGRN);
    pwmeq2xblu : pwm2xeq port map(CLK2X, CLK, CLK2, CLK4, beq2x, DBLU);

    with PWMNR select
    RED <=   rmd    when "000",
             req    when "001",
             rhi    when "010",
             rlo    when "011",
             rmd2x  when "100",
             r2x    when "101",
             rinv2x when "110",
             req2x  when others;

    with PWMNR select
    GRN <=   gmd    when "000",
             geq    when "001",
             ghi    when "010",
             glo    when "011",
             gmd2x  when "100",
             g2x    when "101",
             ginv2x when "110",
             geq2x  when others;

    with PWMNR select
    BLU <=   bmd    when "000",
             beq    when "001",
             bhi    when "010",
             blo    when "011",
             bmd2x  when "100",
             b2x    when "101",
             binv2x when "110",
             beq2x  when others;
end Behavioral;