c2comp.vhd

来自「这个是国外大学的项目代码」· VHDL 代码 · 共 43 行

------------------------------------------------------------------------
--  c2comp.vhd -- Calculate 2's complement
------------------------------------------------------------------------
--  Author : Kovacs Laszlo - Attila 
------------------------------------------------------------------------
-- Software version: Xilinx ISE 7.1.04i
--                   WebPack
------------------------------------------------------------------------
------------------------------------------------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity c2comp is
    Port ( CLK  : in std_logic;
           EN   : in std_logic;
           MASK : in std_logic;
           DI   : in std_logic_vector(15 downto 0);
           DO   : out std_logic_vector(15 downto 0));
end c2comp;

architecture Behavioral of c2comp is

signal res : std_logic_vector(15 downto 0) := "0000000000000000";
signal iDO  : std_logic_vector(15 downto 0) := "0000000000000000";

begin

    DO <= iDO;
    
    process(CLK)
    begin
        if rising_edge(CLK) and EN = '1' then
            iDO <= res;
        end if;
    end process;

    res <= DI when MASK = '0' else (not DI) + 1;

end Behavioral;