epp.vhd

这个是国外大学的项目代码

------------------------------------------------------------------------
--  epp.vhd -- EPP controller
------------------------------------------------------------------------
--  Author : Kovacs Laszlo - Attila 
------------------------------------------------------------------------
-- Software version: Xilinx ISE 7.1.04i
--                   WebPack
------------------------------------------------------------------------
-- EPP controller module. The received register number will determine 
-- the effect of the data received after it, 
-- like: start or end a read or write process, 
-- change image or perform process.
-- The read operation is implemented with ahead reading for faster data 
-- transfer.  
------------------------------------------------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity epp is
    Port ( CLK      : in std_logic;
           --epp
           EPPASTB  : in std_logic;
           EPPDSTB  : in std_logic;
           EPPWRITE : in std_logic;
           EPPRST   : in std_logic;
           EPPWAIT  : out std_logic;
           EPPDB    : inout std_logic_vector(7 downto 0);
           --memory
           EDI      : in std_logic_vector(7 downto 0);
           EDO      : out std_logic_vector(7 downto 0);
           EADR     : out std_logic_vector(19 downto 0);
           EOE      : out std_logic;
           EWR      : out std_logic;
           EBUSY    : out std_logic;
           --ctrl
           EIMGCH   : out std_logic;
           EIMGNR   : out std_logic_vector(3 downto 0);
           EPRCCH   : out std_logic;
           EPRCNR   : out std_logic_vector(2 downto 0);
           --vga
           HDELAY   : out std_logic_vector(2 downto 0);
           VDELAY   : out std_logic_vector(3 downto 0);
           PWMNR    : out std_logic_vector(2 downto 0);
           DSPMODE  : out std_logic_vector(1 downto 0));
end epp;
architecture Behavioral of epp is

-- register effects codes
constant idNOP : std_logic_vector(7 downto 0)       := "00000000";
constant idRDWR : std_logic_vector(7 downto 0)      := "00000001";
constant idRDWREND : std_logic_vector(7 downto 0)   := "00000010";
constant idIMG : std_logic_vector(7 downto 0)       := "00000100";
constant idPRC : std_logic_vector(7 downto 0)       := "00001000";
constant idPWMNR : std_logic_vector(7 downto 0)     := "00010000";
constant idHDELAY : std_logic_vector(7 downto 0)    := "00100000";
constant idVDELAY : std_logic_vector(7 downto 0)    := "01000000";
constant idDSPMODE : std_logic_vector(7 downto 0)   := "10000000";

signal EPPSTB, EPPSTBL, EPPDONE, 
    ADROP, DATAOP, RAMOP, RAMRD, RAMWR, RAMRDWRS : std_logic := '0';
signal oEPPDB, iEPPDB, idADR, ramDATA, ramDATA2 : 
    std_logic_vector(7 downto 0) := "00000000";
signal CNTSTATE, iDSPMODE : std_logic_vector(1 downto 0) := "00";
signal CNTRAM, CNTRAM2 : std_logic := '0';
signal ADR, CNTADR : std_logic_vector(19 downto 0) 
    := "00000000000000000000";
signal sRAMOP, iPRCCH, iIMGCH : std_logic := '0';
signal iIMGNR, iVDELAY : std_logic_vector(3 downto 0) := "0000";
signal iPRCNR, iHDELAY, iPWMNR : std_logic_vector(2 downto 0) := "000";

begin
    
    iEPPDB <= EPPDB;
    EPPDB <= oEPPDB when EPPWRITE = '1' and EPPSTBL = '1' else 
        (others => 'Z');
    EPPWAIT <= EPPDONE;

    oEPPDB <= ramDATA when sRAMOP = '1' else
                 "00000000";

    EDO <= EPPDB;
    EWR <= not RAMWR;
    EOE <= not RAMRD;
    EADR <= ADR;
    EBUSY <= '1' when sRAMOP = '1' or idADR = idRDWR else '0';
    
    EIMGNR <= iIMGNR;
    EPRCNR <= iPRCNR;     
    EPRCCH <= iPRCCH;
    EIMGCH <= iIMGCH;
    HDELAY <= iHDELAY;
    VDELAY <= iVDELAY;
    PWMNR  <= iPWMNR;
    DSPMODE <= iDSPMODE;

    EPPSTB <= EPPASTB and EPPDSTB;
    EPPSTBL <= '1' when CNTSTATE = "01" else '0';
    EPPDONE <= '1' when CNTSTATE = "10" else '0';

    ADROP <= '1' when EPPSTBL = '1' and EPPASTB = '0' else '0';
    DATAOP <= '1' when EPPSTBL = '1' and EPPDSTB = '0' else '0';
    RAMOP <= '1' when RAMRD = '1' or RAMWR = '1' else '0';
    RAMWR <= not EPPWRITE when DATAOP = '1' and sRAMOP = '1' else '0';
    RAMRD <= EPPWRITE when DATAOP = '1' and 
        (sRAMOP = '1' or idADR = idRDWR) else '0';
    RAMRDWRS <= '1' when ADROP = '1' and iEPPDB = idRDWR else '0';
    
    --state couner
    process(CLK, EPPSTB)
    begin
        if EPPSTB = '1' then
            CNTSTATE <= (others => '0');
        elsif rising_edge(CLK) then
            if EPPDONE /= '1' then
                CNTSTATE <= CNTSTATE + 1;
            end if;
        end if;
    end process;
        
    --store address
    process(CLK)
    begin
        if rising_edge(CLK) then    
            if ADROP = '1' then
                idADR <= iEPPDB;
            end if;
        end if;
    end process;
    
    --
    process(CLK)
    begin
        if rising_edge(CLK) then
            iPRCCH <= '0';
            iIMGCH <= '0';
            if DATAOP = '1' and idADR /= idNOP then
                if idADR = idRDWR then
                    sRAMOP <= '1';
                else
                    sRAMOP <= '0';
                end if;
                if idADR = idIMG then
                    iIMGNR <= iEPPDB(3 downto 0);
                    iIMGCH <= '1';
                end if;
                if idADR = idPRC then
                    iPRCNR <= iEPPDB(2 downto 0);
                    iPRCCH <= '1';
                end if;
                if idADR = idPWMNR then
                    iPWMNR <= iEPPDB(2 downto 0);
                end if;
                if idADR = idHDELAY then
                    iHDELAY <= iEPPDB(2 downto 0);
                end if;
                if idADR = idVDELAY then
                    iVDELAY <= iEPPDB(3 downto 0);
                end if;
                if idADR = idDSPMODE then
                    iDSPMODE <= iEPPDB(1 downto 0);
                end if;
            end if;
        end if;
    end process;

    --read ram
    process(CLK)
    begin
        if rising_edge(CLK) then
            CNTRAM <= RAMRD;
            CNTRAM2 <= CNTRAM;
            if CNTRAM2 = '1' then
                ramDATA2 <= EDI;
            end if;
        end if;
    end process;

    --ram address
    process(CLK, RAMRDWRS, EPPRST)
    begin
        if RAMRDWRS = '1' or EPPRST = '0' then
            CNTADR <= (others => '0');
        elsif rising_edge(CLK) then
            if RAMOP = '1' then
                CNTADR <= CNTADR + 1;
            end if;
        end if;
    end process;
    
    --syncronize    
    process(CLK)
    begin
        if rising_edge(CLK) then
            if EPPSTB = '1' then
                ADR <= CNTADR;
                ramDATA <= ramDATA2;
            end if;
        end if;
    end process;
        
end Behavioral;