imgrgb16.vhd

这个是国外大学的项目代码

------------------------------------------------------------------------
--  img.vhd -- RGB Image reading module
------------------------------------------------------------------------
--  Author : Kovacs Laszlo - Attila 
------------------------------------------------------------------------
-- Software version: Xilinx ISE 7.1.04i
--                   WebPack
------------------------------------------------------------------------
-- 2bytes 6:6:4 and 5:6:5 (RGB) bits
-- This reads the image from the memory, in synchron with the vga signal 
-- generator, forwards to the PWM control unit and gives the signals for 
-- the vga port. 
------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;


entity imgrgb16 is
    Port ( CLK   : in std_logic;
           DSPEN : out std_logic;
           --vga 
           VGAHC  : in std_logic_vector(10 downto 0);
           VGAVC  : in std_logic_vector(9 downto 0);
           --pixel data
           DRED  : out std_logic_vector(7 downto 0);
           DGRN  : out std_logic_vector(7 downto 0);
           DBLU  : out std_logic_vector(7 downto 0);
           --data 
           IDI  : in std_logic_vector(7 downto 0);
           IADR : out std_logic_vector(19 downto 0);
           --imgctrl
           SADR : in std_logic_vector(19 downto 0);
           IMGW : in std_logic_vector(10 downto 0);
           IMGH : in std_logic_vector(10 downto 0);
           DSPMODE : in std_logic);
end imgrgb16;

architecture Behavioral of imgrgb16 is

--odd and even addresses
signal oadr : std_logic_vector(19 downto 0) 
    := "00000000000000000000";
--horizntal and vertical in image bounds flags
signal hin, vin : std_logic := '0';
--odd and even data registers
signal opixel, epixel  
    : std_logic_vector(15 downto 0) := "0000000000000000";
signal colorcnt : std_logic_vector(1 downto 0) := "00";
--horizontal display bounds
signal hinc : std_logic_vector(5 downto 0) := "000000";

begin

    hin <= '1' when VGAHC(10 downto 1) < IMGW(9 downto 0) and 
                            IMGW < "01010000001" else '0';
    vin <= '1' when VGAVC(9 downto 0) < IMGH(9 downto 0) and 
                            IMGH < "00111100001" else '0';

    colorcnt <= VGAHC(1 downto 0);

    DSPEN <= '1' when vin = '1' and hinc(0) = '1' else '0';

    process(CLK)
    begin
        if rising_edge(CLK) then
            hinc <= hin & hinc(5 downto 1);
        end if;
    end process;

    process(CLK)
    begin
        if rising_edge(CLK) then
            if DSPMODE = '0' then
                if colorcnt = "01" then
                    dred <= opixel(15 downto 10)&"00";
                    dgrn <= opixel(9 downto 4)&"00";
                    dblu <= opixel(3 downto 0)&"0000";
                elsif colorcnt = "11" then
                    dred <= epixel(15 downto 10)&"00";
                    dgrn <= epixel(9 downto 4)&"00";
                    dblu <= epixel(3 downto 0)&"0000";
                end if;
            else
                if colorcnt = "01" then
                    dred <= opixel(15 downto 11)&"000";
                    dgrn <= opixel(10 downto 5)&"00";
                    dblu <= opixel(4 downto 0)&"000";
                elsif colorcnt = "11" then
                    dred <= epixel(15 downto 11)&"000";
                    dgrn <= epixel(10 downto 5)&"00";
                    dblu <= epixel(4 downto 0)&"000";
                end if;
            end if;
        end if;
    end process;

    --address counters
    process(CLK)
    begin
        if rising_edge(CLK) then
            if hin = '0' and vin = '0' then
                oadr <= SADR;
            elsif hin = '1' and vin = '1' then
                oadr <= oadr + 1;
                IADR <= oadr;
            end if;
        end if;
    end process;

    --fill the odd and even registers with data
    process(CLK)
    begin 
        if rising_edge(CLK) then
            case colorcnt is
            when "11" =>
                opixel(15 downto 8) <= IDI;
            when "00" =>
                opixel(7 downto 0) <= IDI;
            when "01" =>
                epixel(15 downto 8) <= IDI;
            when others =>
                epixel(7 downto 0) <= IDI;
            end case;
        end if;
    end process;

end Behavioral;