sram.syr

这个是国外大学的项目代码

Release 7.1.04i - xst H.42
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.
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--> Reading design: sram.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
  5) Advanced HDL Synthesis
     5.1) HDL Synthesis Report
  6) Low Level Synthesis
  7) Final Report
     7.1) Device utilization summary
     7.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : "sram.prj"
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO

---- Target Parameters
Output File Name                   : "sram"
Output Format                      : NGC
Target Device                      : xc2s200e-6-pq208

---- Source Options
Top Module Name                    : sram
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Style                          : lut
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
ROM Style                          : Auto
Mux Extraction                     : YES
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
Resource Sharing                   : YES
Multiplier Style                   : lut
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 100
Add Generic Clock Buffer(BUFG)     : 4
Register Duplication               : YES
Equivalent register Removal        : YES
Slice Packing                      : YES
Pack IO Registers into IOBs        : auto

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : NO
Global Optimization                : AllClockNets
RTL Output                         : Yes
Write Timing Constraints           : NO
Hierarchy Separator                : /
Bus Delimiter                      : <>
Case Specifier                     : maintain
Slice Utilization Ratio            : 100
Slice Utilization Ratio Delta      : 5

---- Other Options
lso                                : sram.lso
Read Cores                         : YES
cross_clock_analysis               : NO
verilog2001                        : YES
safe_implementation                : No
Optimize Instantiated Primitives   : NO
tristate2logic                     : Yes
use_clock_enable                   : Yes
use_sync_set                       : Yes
use_sync_reset                     : Yes
enable_auto_floorplanning          : No

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "E:/work/digilentinc/XipHard/sram.vhd" in Library work.
Architecture behavioral of Entity sram is up to date.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <sram> (Architecture <behavioral>).
Entity <sram> analyzed. Unit <sram> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <sram>.
    Related source file is "E:/work/digilentinc/XipHard/sram.vhd".
WARNING:Xst:647 - Input <EOE> is never used.
WARNING:Xst:647 - Input <PRD> is never used.
WARNING:Xst:1780 - Signal <iRD> is never used or assigned.
    Found 8-bit register for signal <RAMDB>.
    Found 19-bit register for signal <RAMADR>.
    Found 1-bit register for signal <RAMCS0>.
    Found 1-bit register for signal <RAMCS1>.
    Found 1-bit register for signal <RAMOE>.
    Found 1-bit register for signal <RAMWR>.
    Found 8-bit register for signal <SDO>.
    Found 8-bit tristate buffer for signal <iDATA>.
    Summary:
	inferred  39 D-type flip-flop(s).
	inferred   8 Tristate(s).
Unit <sram> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Advanced Registered AddSub inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Registers                        : 7
 1-bit register                    : 4
 19-bit register                   : 1
 8-bit register                    : 2
# Tristates                        : 1
 8-bit tristate buffer             : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
WARNING:Xst:2042 - Unit sram: 8 internal tristates are replaced by logic (pull-up yes): iDATA<0>, iDATA<1>, iDATA<2>, iDATA<3>, iDATA<4>, iDATA<5>, iDATA<6>, iDATA<7>.

Optimizing unit <sram> ...
Loading device for application Rf_Device from file '2s200e.nph' in environment C:/Program Files/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block sram, actual ratio is 2.
FlipFlop RAMDB_0 has been replicated 1 time(s) to handle iob=true attribute.
FlipFlop RAMDB_1 has been replicated 1 time(s) to handle iob=true attribute.
FlipFlop RAMDB_2 has been replicated 1 time(s) to handle iob=true attribute.
FlipFlop RAMDB_3 has been replicated 1 time(s) to handle iob=true attribute.
FlipFlop RAMDB_4 has been replicated 1 time(s) to handle iob=true attribute.
FlipFlop RAMDB_5 has been replicated 1 time(s) to handle iob=true attribute.
FlipFlop RAMDB_6 has been replicated 1 time(s) to handle iob=true attribute.
FlipFlop RAMDB_7 has been replicated 1 time(s) to handle iob=true attribute.

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : sram.ngr
Top Level Output File Name         : sram
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 164

Macro Statistics :
# Registers                        : 7
#      1-bit register              : 4
#      19-bit register             : 1
#      8-bit register              : 2
# Tristates                        : 1
#      8-bit tristate buffer       : 1

Cell Usage :
# BELS                             : 90
#      INV                         : 1
#      LUT2                        : 20
#      LUT4                        : 68
#      VCC                         : 1
# FlipFlops/Latches                : 47
#      FD                          : 44
#      FDR                         : 2
#      FDS                         : 1
# Clock Buffers                    : 1
#      BUFGP                       : 1
# IO Buffers                       : 161
#      IBUF                        : 122
#      OBUF                        : 39
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s200epq208-6 

 Number of Slices:                      52  out of   2352     2%  
 Number of Slice Flip Flops:            47  out of   4704     0%  
 Number of 4 input LUTs:                88  out of   4704     1%  
 Number of bonded IOBs:                164  out of    146   112% (*) 
 Number of GCLKs:                        1  out of      4    25%  

WARNING:Xst:1336 -  (*) More than 100% of Device resources are used


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
CLK                                | BUFGP                  | 47    |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: 2.636ns (Maximum Frequency: 379.363MHz)
   Minimum input arrival time before clock: 9.268ns
   Maximum output required time after clock: 6.514ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default period analysis for Clock 'CLK'
  Clock period: 2.636ns (frequency: 379.363MHz)
  Total number of paths / destination ports: 8 / 8
-------------------------------------------------------------------------
Delay:               2.636ns (Levels of Logic = 0)
  Source:            RAMDB_7 (FF)
  Destination:       SDO_7 (FF)
  Source Clock:      CLK rising
  Destination Clock: CLK rising

  Data Path: RAMDB_7 to SDO_7
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FD:C->Q               1   0.992   0.920  RAMDB_7 (RAMDB_7)
     FD:D                      0.724          SDO_7
    ----------------------------------------
    Total                      2.636ns (1.716ns logic, 0.920ns route)
                                       (65.1% logic, 34.9% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'CLK'
  Total number of paths / destination ports: 299 / 41
-------------------------------------------------------------------------
Offset:              9.268ns (Levels of Logic = 4)
  Source:            CRD (PAD)
  Destination:       RAMCS1 (FF)
  Destination Clock: CLK rising

  Data Path: CRD to RAMCS1
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O            40   0.797   3.500  CRD_IBUF (CRD_IBUF)
     LUT4:I0->O            1   0.468   0.920  inADR<0>17 (CHOICE312)
     LUT4:I1->O            1   0.468   0.920  inADR<0>30 (CHOICE315)
     LUT4:I1->O            2   0.468   1.150  inADR<0>68 (inADR<0>)
     FDR:R                     0.577          RAMCS1
    ----------------------------------------
    Total                      9.268ns (2.778ns logic, 6.490ns route)
                                       (30.0% logic, 70.0% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'CLK'
  Total number of paths / destination ports: 39 / 39
-------------------------------------------------------------------------
Offset:              6.514ns (Levels of Logic = 1)
  Source:            RAMDB_0_1 (FF)
  Destination:       RAMDB<0> (PAD)
  Source Clock:      CLK rising

  Data Path: RAMDB_0_1 to RAMDB<0>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FD:C->Q               1   0.992   0.920  RAMDB_0_1 (RAMDB_0_1)
     OBUF:I->O                 4.602          RAMDB_0_OBUF (RAMDB<0>)
    ----------------------------------------
    Total                      6.514ns (5.594ns logic, 0.920ns route)
                                       (85.9% logic, 14.1% route)

=========================================================================
CPU : 6.70 / 7.17 s | Elapsed : 7.00 / 7.00 s
 
--> 

Total memory usage is 89800 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :    5 (   0 filtered)
Number of infos    :    0 (   0 filtered)