📄 seg7.vhd
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------------------------------------------------------------------------
-- seg7.vhd -- 7 Segment Controller
------------------------------------------------------------------------
-- Author : Kovacs Laszlo - Attila
------------------------------------------------------------------------
-- Software version: Xilinx ISE 7.1.04i
-- WebPack
------------------------------------------------------------------------
-- Display for the displayed image number, number of images,
-- selected process and the number of processes in the memory.
------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity seg7 is
Port ( CLK : in std_logic;
DATA : in std_logic_vector(15 downto 0);
SEG : out std_logic_vector(6 downto 0);
AN : out std_logic_vector(3 downto 0));
end seg7;
architecture Behavioral of seg7 is
signal HEX : std_logic_vector(3 downto 0) := "0000";
signal cnt : std_logic_vector(18 downto 0) :="0000000000000000000";
begin
process (clk)
begin
if rising_edge(clk) then
cnt <=cnt + 1;
end if;
end process;
with cnt(18 downto 17) select
HEX <= DATA(3 downto 0) when "00",
DATA(7 downto 4) when "01",
DATA(11 downto 8) when "10",
DATA(15 downto 12) when others;
with cnt(18 downto 17) select
AN <= "1110" when "00",
"1101" when "01",
"1011" when "10",
"0111" when others;
with HEX select
SEG<= "1111001" when "0001", --1
"0100100" when "0010", --2
"0110000" when "0011", --3
"0011001" when "0100", --4
"0010010" when "0101", --5
"0000010" when "0110", --6
"1111000" when "0111", --7
"0000000" when "1000", --8
"0010000" when "1001", --9
"0001000" when "1010", --A
"0000011" when "1011", --b
"1000110" when "1100", --C
"0100001" when "1101", --d
"0000110" when "1110", --E
"0001110" when "1111", --F
"1000000" when others; --0
end Behavioral;
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