prc2.vhd

这个是国外大学的项目代码

------------------------------------------------------------------------
--  prc2.vhd -- Image Process Control
------------------------------------------------------------------------
--  Author : Kovacs Laszlo - Attila 
------------------------------------------------------------------------
-- Software version: Xilinx ISE 7.1.04i
--                   WebPack
------------------------------------------------------------------------
-- This module controlls the image processing using a state machine. 
------------------------------------------------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity prc2 is
    Port ( CLK   : in std_logic;
           PRCDO : in std_logic;
           PRCNR : in std_logic_vector(2 downto 0);
           BUSY  : out std_logic;
           --sram
           RD    : out std_logic;
           WR    : out std_logic;
           DI    : in std_logic_vector(7 downto 0);
           DO    : out std_logic_vector(7 downto 0);
           ADR   : out std_logic_vector(19 downto 0));
end prc2;
architecture Behavioral of prc2 is

component conv is
    Port ( CLK      : in std_logic;
           MASK0    : in std_logic_vector(7 downto 0);
           MASK1    : in std_logic_vector(7 downto 0);
           MASK2    : in std_logic_vector(7 downto 0);
           MASK3    : in std_logic_vector(7 downto 0);
           MASK4    : in std_logic_vector(7 downto 0);
           MASK5    : in std_logic_vector(7 downto 0);
           MASK6    : in std_logic_vector(7 downto 0);
           MASK7    : in std_logic_vector(7 downto 0);
           MASK8    : in std_logic_vector(7 downto 0);
           MASK9    : in std_logic_vector(7 downto 0);
           IMGW     : in std_logic_vector(10 downto 0);
           MEN      : in std_logic;
           MVIN     : in std_logic;
           MVOUT    : out std_logic;
           FLINE    : in std_logic;
           LLINE    : in std_logic;
           MDI      : in std_logic_vector(7 downto 0);
           MDO      : out std_logic_vector(7 downto 0));
end component;

component cfifo is
    Port ( CLK    : in std_logic;
           WR     : in std_logic;
           RD     : in std_logic;
           EMPTY  : out std_logic;
           FULL   : out std_logic;
           DI     : in std_logic_vector(7 downto 0);
           DO     : out std_logic_vector(7 downto 0));
end component;

component prcctrl is
    Port ( CLK      : in std_logic;
           EN       : in std_logic;
           DONE     : out std_logic;
           DI       : in std_logic_vector(7 downto 0);
           ADR      : out std_logic_vector(3 downto 0);
           IMGSRC   : out std_logic_vector(3 downto 0);
           IMGDEST  : out std_logic_vector(3 downto 0);
           MASK0    : out std_logic_vector(7 downto 0);
           MASK1    : out std_logic_vector(7 downto 0);
           MASK2    : out std_logic_vector(7 downto 0);
           MASK3    : out std_logic_vector(7 downto 0);
           MASK4    : out std_logic_vector(7 downto 0);
           MASK5    : out std_logic_vector(7 downto 0);
           MASK6    : out std_logic_vector(7 downto 0);
           MASK7    : out std_logic_vector(7 downto 0);
           MASK8    : out std_logic_vector(7 downto 0);
           MASK9    : out std_logic_vector(7 downto 0));
end component;

component imgctrl2 is
    Port ( CLK     : in std_logic;
           EN      : in std_logic;
           DONE    : out std_logic;
           DI      : in std_logic_vector(7 downto 0);
           ADR     : out std_logic_vector(2 downto 0);
           IMGW    : out std_logic_vector(10 downto 0);
           IMGH    : out std_logic_vector(10 downto 0);
           IMGADR  : out std_logic_vector(19 downto 0));
end component;

--FSM states
type statetype is (IDLE, RDPRC, RDSRC, RDDEST, PRCSTART, RDSTART, 
                   RDDATA, RDEND, WRDATASTART, WRDATA, WRDATAEND);
--state register
signal state, nextstate : statetype := IDLE;
--internal output signals
signal fBUSY,fRDPRC,fRDSRC,fRDDEST,fPRCSTART,fRDSTART,fRDEND,fRDDATA,
    fPROCESS,fRDBUFF,fWRDATA : std_logic := '0';
--FSM output signals
signal iBUSY,iRDPRC,iRDSRC,iRDDEST,iPRCSTART,iRDSTART,iRDEND,iRDDATA,
    iPROCESS,iRDBUFF,iWRDATA : std_logic := '0';
--some operation end signals
signal RDPRCDONE,RDSRCDONE,RDDESTDONE,RDDATADONE,PRCDONE 
    : std_logic := '0';
--process number register
signal iPRCNR : std_logic_vector(2 downto 0) := "000";
--convolution mask constants (multipliers and divider)
signal MASK0,MASK1,MASK2,MASK3,MASK4,MASK5,MASK6,MASK7,MASK8,MASK9:
    std_logic_vector(7 downto 0) := "00000000" ;
--source and destination image number register
signal IMGSRC, IMGDEST : std_logic_vector(3 downto 0) := "0000";
signal RDPRCADR : std_logic_vector(3 downto 0) := "0000";
signal RDSRCADR, RDDESTADR : std_logic_vector(2 downto 0) := "000";
signal SRCADR, DESTADR : std_logic_vector(19 downto 0) := 
    "00000000000000000000";
signal IMGW, IMGH : std_logic_vector(10 downto 0) := "00000000000";
signal CWIDTH, CHEIGHT : std_logic_vector(10 downto 0) := 
    "00000000000";
signal CSRCADR, CDESTADR : std_logic_vector(19 downto 0) := 
    "00000000000000000000";
signal CONVEN, CONVVIN, CONVVOUT, FIFOWR, FIFORD, FIFOEMPTY,
     FIFOFULL, FLINE, LLINE : std_logic := '0';
signal CONVDO : std_logic_vector(7 downto 0) := "00000000";
signal COLOR, CCOLOR : std_logic_vector(1 downto 0) := "00";

begin

    RD <= iRDPRC or iRDSRC or iRDDEST or iRDDATA;
    WR <= iWRDATA;
    BUSY <= iBUSY;
    ADR <= "0000000000001"&(iPRCNR-1)&RDPRCADR when iRDPRC = '1'  else
           "0000000000000"&IMGSRC&RDSRCADR     when iRDSRC = '1'  else
           "0000000000000"&IMGDEST&RDDESTADR   when iRDDEST = '1' else
           csrcadr                             when iRDDATA = '1' else
           cdestadr;
    CONVEN <= iPROCESS;
    CONVVIN <= '1' when PRCDONE = '0' and FLINE = '0' else '0';
    FIFOWR <= iPROCESS and CONVVOUT;
    FIFORD <= iRDBUFF;
    FLINE <= '1' when CHEIGHT = "00000000000" else '0';
    LLINE <= RDDATADONE;

    sRDPRC:prcctrl port map(
        CLK, iRDPRC, RDPRCDONE, DI, RDPRCADR, IMGSRC, IMGDEST, 
        MASK0, MASK1, MASK2, MASK3, MASK4, 
        MASK5, MASK6, MASK7, MASK8, MASK9);
    sRDSRC:imgctrl2 port map(
        CLK, iRDSRC, RDSRCDONE, DI, RDSRCADR, IMGW, IMGH, SRCADR);
    sRDDEST:imgctrl2 port map(
        CLK, iRDDEST, RDDESTDONE, DI, RDDESTADR, open, open, DESTADR);
    sCONV:conv port map(
        CLK, MASK0, MASK1, MASK2, MASK3, MASK4, 
        MASK5, MASK6, MASK7, MASK8, MASK9, 
        IMGW, CONVEN, CONVVIN, CONVVOUT, FLINE, LLINE, DI, CONVDO);
    SFIFO:cfifo port map(
        CLK, FIFOWR, FIFORD, FIFOEMPTY, FIFOFULL, CONVDO, DO);
    
    process(CLK)
    begin
        if rising_edge(CLK) then
            if PRCDO = '1' then
                iPRCNR <= PRCNR;
            end if;
        end if;
    end process;

    COLOR <= "11";
    process(CLK, iRDSRC)
    begin
        if iRDSRC = '1' then
            CCOLOR <= (others => '0');
        elsif rising_edge(CLK) then
            if iPRCSTART = '1' then
                CCOLOR <= CCOLOR + 1;
            end if;
        end if;
    end process;


    --source address counter
    process(CLK)
    begin
        if rising_edge(CLK) then
            if iPRCSTART = '1' then
                CSRCADR <= SRCADR + CCOLOR;
            elsif iRDDATA = '1' and PRCDONE = '0' then
                CSRCADR <= CSRCADR + 3;
            end if;
        end if;
    end process;    

    --destination address counter
    process(CLK)
    begin
        if rising_edge(CLK) then
            if iPRCSTART = '1' then
                CDESTADR <= DESTADR + CCOLOR;
            elsif iWRDATA = '1' then
                CDESTADR <= CDESTADR + 3;
            end if;
        end if;
    end process;    

    --image width counter
    process(CLK)
    begin    
        if rising_edge(CLK) then
            if (iRDDATA = '1' and PRCDONE = '0') or 
                iPRCSTART = '1' then
                if CWIDTH = IMGW or iPRCSTART = '1' then
                    CWIDTH <= "00000000001";
                else
                    CWIDTH <= cwidth + 1;
                end if;
            end if;
        end if;
    end process;    

    --image height counter
    process(CLK, iPRCSTART)
    begin
        if rising_edge(CLK) then
            if (iRDDATA = '1' and CWIDTH = IMGW and PRCDONE = '0') or 
                iPRCSTART = '1' then
                if iPRCSTART = '1' then
                    CHEIGHT <= "00000000000";
                else
                    cheight <= cheight + 1;
                end if;
            end if;
        end if;
    end process;

    RDDATADONE <= '1' when cheight = IMGH else '0';
    PRCDONE <= '1' when cheight = IMGH + 1 else '0';
    

    SYNC_PROC: process(CLK)
    begin
        if rising_edge(CLK) then
            state <= nextstate;
            iBUSY <= fBUSY;
            iRDPRC <= fRDPRC;
            iRDSRC <= fRDSRC;
            iRDDEST <= fRDDEST;
            iPRCSTART <= fPRCSTART;
            iRDDATA <= fRDDATA;
            iPROCESS <= fPROCESS;
            iRDBUFF <= fRDBUFF;
            iWRDATA <= fWRDATA;
            iRDSTART <= fRDSTART;
            iRDEND <= fRDEND;
        end if;
    end process;
    
    OUTPUT_DECODE: process(state)
    begin    
        if state = IDLE then
            fBUSY <= '0';
        else
            fBUSY <= '1';
        end if;
        if state = RDPRC then
            fRDPRC <= '1';
        else
            fRDPRC <= '0';
        end if;
        if state = RDSRC then
            fRDSRC <= '1';
        else
            fRDSRC <= '0';
        end if;
        if state = RDDEST then
            fRDDEST <= '1';
        else
            fRDDEST <= '0';
        end if;
        if state = PRCSTART then
            fPRCSTART <= '1';
        else
            fPRCSTART <= '0';
        end if;
        if state = RDSTART then
            fRDSTART <= '1';
        else
            fRDSTART <= '0';
        end if;
        if state = RDDATA or state = RDSTART then
            fRDDATA <= '1';
        else
            fRDDATA <= '0';
        end if;
        if state = RDEND then
            fRDEND <= '1';
        else
            fRDEND <= '0';
        end if;
        if state = RDDATA or state = RDEND then
            fPROCESS <= '1';
        else
            fPROCESS <= '0';
        end if;
        if state = WRDATA or state = WRDATASTART then
            fRDBUFF <= '1';
        else
            fRDBUFF <= '0';
        end if;
        if state = WRDATA or state = WRDATAEND then
            fWRDATA <= '1';
        else
            fWRDATA <= '0';
        end if;
    end process; 

    NEXT_STATE_DECODE: process(state, iPRCNR, PRCNR, RDPRCDONE, 
        RDSRCDONE, RDDESTDONE, iRDSTART, iRDEND, PRCDONE, FIFOFULL, 
        FIFOEMPTY, PRCDO, COLOR, CCOLOR, CONVVOUT)
    begin    
        nextstate <= state;
        case state is
            when IDLE =>
                if PRCDO = '1' then
                    nextstate <= RDPRC;
                end if;
            when RDPRC =>
                if RDPRCDONE = '1' then 
                    nextstate <= RDSRC;
                end if;
            when RDSRC =>
                if RDSRCDONE = '1' then 
                    nextstate <= RDDEST;
                end if;
            when RDDEST =>
                if RDDESTDONE = '1' then
                    nextstate <= PRCSTART;
                end if;
            when PRCSTART =>
                nextstate <= RDSTART;
            when RDSTART =>
                if iRDSTART = '1' then
                    nextstate <= RDDATA;
                end if;
            when RDDATA =>
                if (PRCDONE = '1' and CONVVOUT = '0') or  
                    FIFOFULL = '1' then
                    nextstate <= RDEND;
                end if;
            when RDEND =>
                if iRDEND = '1' then
                    nextstate <= WRDATASTART;
                end if;
            when WRDATASTART =>
                nextstate <= WRDATA;
            when WRDATA =>
                if FIFOEMPTY = '1' then
                    nextstate <= WRDATAEND;
                end if;
            when WRDATAEND =>
                if PRCDONE = '1' and CONVVOUT = '0' then
                    if COLOR = CCOLOR then
                        nextstate <= IDLE;
                    else
                        nextstate <= PRCSTART;
                    end if;
                else
                    nextstate <= RDSTART;
                end if;
            when others =>
                nextstate <= IDLE;
        end case;
    end process; 

end Behavioral;