cround.vhd

来自「这个是国外大学的项目代码」· VHDL 代码 · 共 47 行

------------------------------------------------------------------------
--  cround.vhd -- Checking the result
------------------------------------------------------------------------
--  Author : Kovacs Laszlo - Attila 
------------------------------------------------------------------------
-- Software version: Xilinx ISE 7.1.04i
--                   WebPack
------------------------------------------------------------------------
------------------------------------------------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity cround is
    Port ( CLK  : in std_logic;
           EN   : in std_logic;
           MASK : in std_logic;
           DI   : in std_logic_vector(15 downto 0);
           DO   : out std_logic_vector(7 downto 0));
end cround;

architecture Behavioral of cround is

signal res, res2 : std_logic_vector(7 downto 0) := "00000000";
signal iDO : std_logic_vector(7 downto 0) := "00000000";

begin

    DO <= iDO;
    
    process(CLK)
    begin
        if rising_edge(CLK) and EN = '1' then
            iDO <= res2;
        end if;
    end process;

    res <= (others => '0') when DI(15) = '1' else
            (others => '1') when DI(14 downto 8) /= "0000000" else
            DI(7 downto 0);

    res2 <= res when MASK = '0' else not res;

end Behavioral;