img.vhd

这个是国外大学的项目代码

------------------------------------------------------------------------
--  img.vhd -- Image display module
------------------------------------------------------------------------
--  Author : Kovacs Laszlo - Attila 
------------------------------------------------------------------------
-- Software version: Xilinx ISE 7.1.04i
--                   WebPack
------------------------------------------------------------------------
-- The img controlles the image display. Contains image reders 
-- clock generator, vga signal generator and 
-- pulse width modulator modules.
------------------------------------------------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity img is
    Port ( CLK  : in std_logic;
           --vga signal
           RED  : out std_logic;
           GRN  : out std_logic;
           BLU  : out std_logic;
           HS   : out std_logic;
           VS   : out std_logic;
           --epp 
           EBUSY : in std_logic;
           --data 
           IDI  : in std_logic_vector(7 downto 0);
           IADR : out std_logic_vector(19 downto 0);
           --ctrl
           SWT  : in std_logic_vector(7 downto 0);
           --imgctrl
           SADR : in std_logic_vector(19 downto 0);
           IMGW : in std_logic_vector(10 downto 0);
           IMGH : in std_logic_vector(10 downto 0);
           --vga
           HDELAY   : in std_logic_vector(2 downto 0);
           VDELAY   : in std_logic_vector(3 downto 0);
           PWMNR    : in std_logic_vector(2 downto 0);
           DSPMODE  : in std_logic_vector(1 downto 0));
end img;
architecture Behavioral of img is

component clkgen is
    Port ( CLK   : in std_logic;
           CLK2X : out std_logic;
           CLK2  : out std_logic;
           CLK4  : out std_logic;
           CLK8  : out std_logic);
end component;

component vga is
    Port ( CLK    : in std_logic;
           VGAHS  : out std_logic;
           VGAVS  : out std_logic;
           VGADSP : out std_logic;
           VGAHC  : out std_logic_vector(10 downto 0);
           VGAVC  : out std_logic_vector(9 downto 0);
           HDELAY  : in std_logic_vector(2 downto 0);
           VDELAY  : in std_logic_vector(3 downto 0));
end component;

component pixel is
    Port ( CLK   : in std_logic;
           CLK2X : in std_logic;
           CLK2  : in std_logic;
           CLK4  : in std_logic;
           CLK8  : in std_logic;
           RED   : out std_logic;
           GRN   : out std_logic;
           BLU   : out std_logic;
           DRED  : in std_logic_vector(7 downto 0);
           DGRN  : in std_logic_vector(7 downto 0);
           DBLU  : in std_logic_vector(7 downto 0);
           PWMNR : in std_logic_vector(2 downto 0));
end component;

component imgrgb24 is
    Port ( CLK   : in std_logic;
           DSPEN : out std_logic;
           --vga 
           VGAHC  : in std_logic_vector(10 downto 0);
           VGAVC  : in std_logic_vector(9 downto 0);
           --pixel data
           DRED  : out std_logic_vector(7 downto 0);
           DGRN  : out std_logic_vector(7 downto 0);
           DBLU  : out std_logic_vector(7 downto 0);
           --data 
           IDI  : in std_logic_vector(7 downto 0);
           IADR : out std_logic_vector(19 downto 0);
           --imgctrl
           SADR : in std_logic_vector(19 downto 0);
           IMGW : in std_logic_vector(10 downto 0);
           IMGH : in std_logic_vector(10 downto 0));
end component;

component imgrgb16 is
    Port ( CLK   : in std_logic;
           DSPEN : out std_logic;
           --vga 
           VGAHC  : in std_logic_vector(10 downto 0);
           VGAVC  : in std_logic_vector(9 downto 0);
           --pixel data
           DRED  : out std_logic_vector(7 downto 0);
           DGRN  : out std_logic_vector(7 downto 0);
           DBLU  : out std_logic_vector(7 downto 0);
           --data 
           IDI  : in std_logic_vector(7 downto 0);
           IADR : out std_logic_vector(19 downto 0);
           --imgctrl
           SADR : in std_logic_vector(19 downto 0);
           IMGW : in std_logic_vector(10 downto 0);
           IMGH : in std_logic_vector(10 downto 0);
           DSPMODE : in std_logic);
end component;

--clock signals 
signal CLK2X, CLK2, CLK4, CLK8 : std_logic := '0';
--hrizontal and vertical conter numbers from the vga controller
signal VGAHC : std_logic_vector(10 downto 0) := "00000000000";
signal VGAVC : std_logic_vector(9 downto 0) := "0000000000";
--VGA syncronization signals
signal VGAHS, VGAVS, VGADSP : std_logic := '0';
--internal color signals
signal VRED, VGRN, VBLU : std_logic := '0';
--horizontal display end
signal hinc : std_logic_vector(7 downto 0) := "00000000";
--
signal DSPEN24, DSPEN16 : std_logic := '0';
signal DRED, DGRN, DBLU, DRED24, DGRN24, DBLU24, DRED16, DGRN16, DBLU16
    : std_logic_vector(7 downto 0) := "00000000";
signal IADR24, IADR16 : std_logic_vector(19 downto 0) 
    := "00000000000000000000";

begin
                                                                
    --VGA signal generator
    vga0 : vga port map(
        CLK, VGAHS, VGAVS, VGADSP, VGAHC, VGAVC, HDELAY, VDELAY);
    --clock generator
    clkgen0 : clkgen port map(
        CLK, CLK2X, CLK2, CLK4, CLK8);
    --pwm demultiplexer module
    pixel0 : pixel port map(
        CLK, CLK2X, CLK2, CLK4, CLK8, VRED, VGRN, VBLU, 
        DRED, DGRN, DBLU, PWMNR);
    --display for image with RGB 24bit pixels
    imgrgb24b : imgrgb24 port map(
        CLK, DSPEN24, VGAHC, VGAVC, DRED24, DGRN24, DBLU24, 
        IDI, IADR24, SADR, IMGW, IMGH);
    --display for image with RGB 6:6:4 16bit pixels
    imgrgb16b : imgrgb16 port map(
        CLK, DSPEN16, VGAHC, VGAVC, DRED16, DGRN16, DBLU16, 
        IDI, IADR16, SADR, IMGW, IMGH, DSPMODE(1));

    IADR <= IADR24 when DSPMODE(0) = '0' else IADR16;

    HS <= VGAHS;
    VS <= VGAVS;

    RED <= VRED when (DSPMODE(0) = '0' and DSPEN24 = '1') or 
                (DSPMODE(0) = '1' and DSPEN16 = '1') or
                (VGADSP = '1' and SWT(7 downto 5) /= "000") else '0';
    GRN <= VGRN when (DSPMODE(0) = '0' and DSPEN24 = '1') or 
                (DSPMODE(0) = '1' and DSPEN16 = '1') or
                (VGADSP = '1' and SWT(7 downto 5) /= "000")  else '0';
    BLU <= VBLU when (DSPMODE(0) = '0' and DSPEN24 = '1') or 
                (DSPMODE(0) = '1' and DSPEN16 = '1') or
                (VGADSP = '1' and SWT(7 downto 5) /= "000") else '0';

    DRED <= VGAVC(7 downto 0) when SWT(7) = '1' else
            "00000000" when SWT(7 downto 5) /= "000" else
            "00000000" when EBUSY = '1' else
            DRED24 when DSPMODE(0) = '0' else
            DRED16;

    DGRN <= VGAVC(7 downto 0) when SWT(6) = '1' else
            "00000000" when SWT(7 downto 5) /= "000" else
            (others => VGAHC(2)) when EBUSY = '1' else
            DGRN24 when DSPMODE(0) = '0' else
            DGRN16;

    DBLU <= VGAVC(7 downto 0) when SWT(5) = '1' else
            "00000000" when SWT(7 downto 5) /= "000" else
            (others => VGAHC(2)) when EBUSY = '1' else
            DBLU24 when DSPMODE(0) = '0' else
            DBLU16;

             

end Behavioral;