cbuff.vhd

这个是国外大学的项目代码

------------------------------------------------------------------------
--  cbuff.vhd -- Line Buffer
------------------------------------------------------------------------
--  Author : Kovacs Laszlo - Attila 
------------------------------------------------------------------------
-- Software version: Xilinx ISE 7.1.04i
--                   WebPack
------------------------------------------------------------------------
-- This module is a buffer to hold a line of the image. 
-- The byte on the input of the unit is available on the output 
-- after width - 2 enabled clock cycles. 
-- With 4 dual-port blockrams can process images up to 2048 width.
------------------------------------------------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

library UNISIM;
use UNISIM.VComponents.all;

entity cbuff is
    Port ( CLK   : in std_logic;
           EN    : in std_logic;
           DI    : in std_logic_vector(7 downto 0);
           DO    : out std_logic_vector(7 downto 0);
           WIDTH : in std_logic_vector(10 downto 0));
end cbuff;

architecture Behavioral of cbuff is

signal rdaddr : std_logic_vector(10 downto 0) := "00000000000";
signal wraddr : std_logic_vector(10 downto 0) := "00000000011";
signal rdaddrcs0 : std_logic_vector(1 downto 0) := "00";
signal iWIDTH : std_logic_vector(10 downto 0) := "00000000011";
signal DO0, DO1, DO2, DO3 : std_logic_vector(7 downto 0) := "00000000";
signal EN0, EN1, EN2, EN3 : std_logic := '0';

begin

    process(clk)
    begin
        if rising_edge(CLK) then
            if iWIDTH /= WIDTH then
                iWIDTH <= WIDTH;
                rdaddr <= "00000000011";
                wraddr <= WIDTH;
            elsif en = '1' then
                rdaddr <= rdaddr + 1;
                wraddr <= wraddr + 1;
                rdaddrcs0 <= rdaddr(10 downto 9);
            end if;
        end if;
    end process;
    
    with rdaddrcs0 select 
    DO <= DO0 when "00",
          DO1 when "01",
          DO2 when "10",
          DO3 when others;
    
    EN0 <= EN when wraddr(10 downto 9) = "00" else '0';
    EN1 <= EN when wraddr(10 downto 9) = "01" else '0';
    EN2 <= EN when wraddr(10 downto 9) = "10" else '0';
    EN3 <= EN when wraddr(10 downto 9) = "11" else '0';

   RAMB4_S8_S8_inst0 : RAMB4_S8_S8
   generic map (
      INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000")
   port map (
      DOA => open,
      DOB => DO0, 
      ADDRA => wraddr(8 downto 0),
      ADDRB => rdaddr(8 downto 0),
      CLKA => CLK,   
      CLKB => CLK,   
      DIA => DI,
      DIB => "00000000",
      ENA => '1',
      ENB => '1',     
      RSTA => '1',   
      RSTB => '0',   
      WEA => EN0,    
      WEB => '0'     
   ); 

   RAMB4_S8_S8_inst1 : RAMB4_S8_S8
   generic map (
      INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000")
   port map (
      DOA => open,
      DOB => DO1, 
      ADDRA => wraddr(8 downto 0),
      ADDRB => rdaddr(8 downto 0),
      CLKA => CLK,   
      CLKB => CLK,   
      DIA => DI,
      DIB => "00000000",
      ENA => '1',
      ENB => '1',     
      RSTA => '1',   
      RSTB => '0',   
      WEA => EN1,    
      WEB => '0'     
   ); 

   RAMB4_S8_S8_inst2 : RAMB4_S8_S8
   generic map (
      INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000")
   port map (
      DOA => open,
      DOB => DO2, 
      ADDRA => wraddr(8 downto 0),
      ADDRB => rdaddr(8 downto 0),
      CLKA => CLK,   
      CLKB => CLK,   
      DIA => DI,
      DIB => "00000000",
      ENA => '1',
      ENB => '1',     
      RSTA => '1',   
      RSTB => '0',   
      WEA => EN2,    
      WEB => '0'     
   ); 

   RAMB4_S8_S8_inst3 : RAMB4_S8_S8
   generic map (
      INIT_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
      INIT_0F => X"0000000000000000000000000000000000000000000000000000000000000000")
   port map (
      DOA => open,
      DOB => DO3, 
      ADDRA => wraddr(8 downto 0),
      ADDRB => rdaddr(8 downto 0),
      CLKA => CLK,   
      CLKB => CLK,   
      DIA => DI,
      DIB => "00000000",
      ENA => '1',
      ENB => '1',     
      RSTA => '1',   
      RSTB => '0',   
      WEA => EN3,    
      WEB => '0'     
   ); 

end Behavioral;