conv.syr

这个是国外大学的项目代码

    Found 10-bit shift register for signal <valid<9>>.
    Summary:
	inferred   1 Shift register(s).
Unit <conv> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Advanced Registered AddSub inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Adders/Subtractors               : 17
 16-bit adder                      : 17
# Counters                         : 4
 11-bit up counter                 : 4
# Registers                        : 42
 11-bit register                   : 2
 16-bit register                   : 30
 2-bit register                    : 2
 8-bit register                    : 8
# Shift Registers                  : 1
 10-bit shift register             : 1
# Comparators                      : 2
 11-bit comparator not equal       : 2
# Multiplexers                     : 3
 8-bit 4-to-1 multiplexer          : 3

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
WARNING:Xst:1293 - FF/Latch  <iDO_15> has a constant value of 0 in block <cmul>.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch  <iDO_13> has a constant value of 0 in block <cmul>.
WARNING:Xst:1896 - Due to other FF/Latch trimming, FF/Latch  <iDO_14> has a constant value of 0 in block <cmul>.

Optimizing unit <conv> ...

Optimizing unit <clog> ...

Optimizing unit <cbuff> ...

Optimizing unit <cround> ...

Optimizing unit <cdiv> ...

Optimizing unit <cmul> ...

Optimizing unit <c2comp> ...
Loading device for application Rf_Device from file '2s200e.nph' in environment C:/Program Files/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block conv, actual ratio is 24.

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : conv.ngr
Top Level Output File Name         : conv
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 112

Macro Statistics :
# Registers                        : 46
#      11-bit register             : 6
#      16-bit register             : 30
#      2-bit register              : 2
#      8-bit register              : 8
# Shift Registers                  : 1
#      10-bit shift register       : 1
# Multiplexers                     : 3
#      8-bit 4-to-1 multiplexer    : 3
# Adders/Subtractors               : 21
#      11-bit adder                : 4
#      16-bit adder                : 17
# Comparators                      : 2
#      11-bit comparator not equal : 2

Cell Usage :
# BELS                             : 1650
#      BUF                         : 5
#      GND                         : 1
#      INV                         : 112
#      LUT1                        : 31
#      LUT1_L                      : 27
#      LUT2                        : 141
#      LUT2_L                      : 14
#      LUT3                        : 158
#      LUT3_L                      : 203
#      LUT4                        : 188
#      LUT4_L                      : 60
#      MUXCY                       : 307
#      MUXF5                       : 107
#      VCC                         : 1
#      XORCY                       : 295
# FlipFlops/Latches                : 588
#      FDE                         : 566
#      FDRE                        : 18
#      FDSE                        : 4
# RAMS                             : 8
#      RAMB4_S8_S8                 : 8
# Shifters                         : 1
#      SRL16E                      : 1
# Clock Buffers                    : 1
#      BUFGP                       : 1
# IO Buffers                       : 111
#      IBUF                        : 102
#      OBUF                        : 9
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s200epq208-6 

 Number of Slices:                     525  out of   2352    22%  
 Number of Slice Flip Flops:           588  out of   4704    12%  
 Number of 4 input LUTs:               823  out of   4704    17%  
 Number of bonded IOBs:                112  out of    146    76%  
 Number of BRAMs:                        8  out of     14    57%  
 Number of GCLKs:                        1  out of      4    25%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
CLK                                | BUFGP                  | 597   |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: 10.112ns (Maximum Frequency: 98.892MHz)
   Minimum input arrival time before clock: 14.431ns
   Maximum output required time after clock: 6.514ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default period analysis for Clock 'CLK'
  Clock period: 10.112ns (frequency: 98.892MHz)
  Total number of paths / destination ports: 7291 / 844
-------------------------------------------------------------------------
Delay:               10.112ns (Levels of Logic = 5)
  Source:            buffb/RAMB4_S8_S8_inst0 (RAM)
  Destination:       mul6/iDO_4 (FF)
  Source Clock:      CLK rising
  Destination Clock: CLK rising

  Data Path: buffb/RAMB4_S8_S8_inst0 to mul6/iDO_4
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     RAMB4_S8_S8:CLKB->DOB2    1   3.220   0.920  buffb/RAMB4_S8_S8_inst0 (buffb/DO0<2>)
     LUT3_L:I1->LO         1   0.468   0.000  buffb/Mmux_DO_DO<0>_DO<0>_rn_0111_F (N2827)
     MUXF5:I0->O           6   0.422   1.850  buffb/Mmux_DO_DO<0>_DO<0>_rn_0111 (w31<2>)
     LUT3:I1->O            2   0.468   1.150  mul6/res<4>21 (mul6/N01)
     LUT4_L:I1->LO         1   0.468   0.000  mul6/res<4>143_F (N3021)
     MUXF5:I0->O           1   0.422   0.000  mul6/res<4>143 (mul6/res<4>)
     FDE:D                     0.724          mul6/iDO_4
    ----------------------------------------
    Total                     10.112ns (6.192ns logic, 3.920ns route)
                                       (61.2% logic, 38.8% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'CLK'
  Total number of paths / destination ports: 5672 / 963
-------------------------------------------------------------------------
Offset:              14.431ns (Levels of Logic = 3)
  Source:            MEN (PAD)
  Destination:       buffb/RAMB4_S8_S8_inst0 (RAM)
  Destination Clock: CLK rising

  Data Path: MEN to buffb/RAMB4_S8_S8_inst0
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O            93   0.797   4.825  MEN_IBUF (MEN_IBUF)
     BUF:I->O             93   0.468   4.825  MEN_IBUF_5 (MEN_IBUF_5)
     LUT3:I0->O            1   0.468   0.920  buffb/EN31 (buffb/EN3)
     RAMB4_S8_S8:WEA           2.128          buffb/RAMB4_S8_S8_inst3
    ----------------------------------------
    Total                     14.431ns (3.861ns logic, 10.570ns route)
                                       (26.8% logic, 73.2% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'CLK'
  Total number of paths / destination ports: 9 / 9
-------------------------------------------------------------------------
Offset:              6.514ns (Levels of Logic = 1)
  Source:            Mshreg_valid<9>_0 (FF)
  Destination:       MVOUT (PAD)
  Source Clock:      CLK rising

  Data Path: Mshreg_valid<9>_0 to MVOUT
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDE:C->Q              1   0.992   0.920  Mshreg_valid<9>_0 (Mshreg_valid<9>_0)
     OBUF:I->O                 4.602          MVOUT_OBUF (MVOUT)
    ----------------------------------------
    Total                      6.514ns (5.594ns logic, 0.920ns route)
                                       (85.9% logic, 14.1% route)

=========================================================================
CPU : 25.19 / 25.70 s | Elapsed : 25.00 / 25.00 s
 
--> 

Total memory usage is 101064 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :    5 (   0 filtered)
Number of infos    :    0 (   0 filtered)