conv.syr

这个是国外大学的项目代码

Release 7.1.04i - xst H.42
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to __projnav
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--> Parameter xsthdpdir set to ./xst
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--> Reading design: conv.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
  5) Advanced HDL Synthesis
     5.1) HDL Synthesis Report
  6) Low Level Synthesis
  7) Final Report
     7.1) Device utilization summary
     7.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : "conv.prj"
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO

---- Target Parameters
Output File Name                   : "conv"
Output Format                      : NGC
Target Device                      : xc2s200e-6-pq208

---- Source Options
Top Module Name                    : conv
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Style                          : lut
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
ROM Style                          : Auto
Mux Extraction                     : YES
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
Resource Sharing                   : YES
Multiplier Style                   : lut
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 100
Add Generic Clock Buffer(BUFG)     : 4
Register Duplication               : YES
Equivalent register Removal        : YES
Slice Packing                      : YES
Pack IO Registers into IOBs        : auto

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : NO
Global Optimization                : AllClockNets
RTL Output                         : Yes
Write Timing Constraints           : NO
Hierarchy Separator                : /
Bus Delimiter                      : <>
Case Specifier                     : maintain
Slice Utilization Ratio            : 100
Slice Utilization Ratio Delta      : 5

---- Other Options
lso                                : conv.lso
Read Cores                         : YES
cross_clock_analysis               : NO
verilog2001                        : YES
safe_implementation                : No
Optimize Instantiated Primitives   : NO
tristate2logic                     : Yes
use_clock_enable                   : Yes
use_sync_set                       : Yes
use_sync_reset                     : Yes
enable_auto_floorplanning          : No

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "E:/work/digilentinc/XipHard/clog.vhd" in Library work.
Architecture behavioral of Entity clog is up to date.
Compiling vhdl file "E:/work/digilentinc/XipHard/creg.vhd" in Library work.
Architecture behavioral of Entity creg is up to date.
Compiling vhdl file "E:/work/digilentinc/XipHard/cbuff.vhd" in Library work.
Architecture behavioral of Entity cbuff is up to date.
Compiling vhdl file "E:/work/digilentinc/XipHard/cmul.vhd" in Library work.
Architecture behavioral of Entity cmul is up to date.
Compiling vhdl file "E:/work/digilentinc/XipHard/c2comp.vhd" in Library work.
Architecture behavioral of Entity c2comp is up to date.
Compiling vhdl file "E:/work/digilentinc/XipHard/cadd.vhd" in Library work.
Architecture behavioral of Entity cadd is up to date.
Compiling vhdl file "E:/work/digilentinc/XipHard/cnop.vhd" in Library work.
Architecture behavioral of Entity cnop is up to date.
Compiling vhdl file "E:/work/digilentinc/XipHard/cdiv.vhd" in Library work.
Architecture behavioral of Entity cdiv is up to date.
Compiling vhdl file "E:/work/digilentinc/XipHard/cround.vhd" in Library work.
Entity <cround> compiled.
Entity <cround> (Architecture <behavioral>) compiled.
Compiling vhdl file "E:/work/digilentinc/XipHard/conv.vhd" in Library work.
Architecture behavioral of Entity conv is up to date.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <conv> (Architecture <behavioral>).
Entity <conv> analyzed. Unit <conv> generated.

Analyzing Entity <clog> (Architecture <behavioral>).
Entity <clog> analyzed. Unit <clog> generated.

Analyzing Entity <creg> (Architecture <behavioral>).
Entity <creg> analyzed. Unit <creg> generated.

Analyzing Entity <cbuff> (Architecture <behavioral>).
Entity <cbuff> analyzed. Unit <cbuff> generated.

Analyzing Entity <cmul> (Architecture <behavioral>).
Entity <cmul> analyzed. Unit <cmul> generated.

Analyzing Entity <c2comp> (Architecture <behavioral>).
Entity <c2comp> analyzed. Unit <c2comp> generated.

Analyzing Entity <cadd> (Architecture <behavioral>).
Entity <cadd> analyzed. Unit <cadd> generated.

Analyzing Entity <cnop> (Architecture <behavioral>).
Entity <cnop> analyzed. Unit <cnop> generated.

Analyzing Entity <cdiv> (Architecture <behavioral>).
Entity <cdiv> analyzed. Unit <cdiv> generated.

Analyzing Entity <cround> (Architecture <behavioral>).
Entity <cround> analyzed. Unit <cround> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <cround>.
    Related source file is "E:/work/digilentinc/XipHard/cround.vhd".
    Found 8-bit register for signal <iDO>.
    Found 8-bit 4-to-1 multiplexer for signal <res>.
    Summary:
	inferred   8 D-type flip-flop(s).
	inferred   8 Multiplexer(s).
Unit <cround> synthesized.


Synthesizing Unit <cdiv>.
    Related source file is "E:/work/digilentinc/XipHard/cdiv.vhd".
WARNING:Xst:647 - Input <MASK<3>> is never used.
    Found 16-bit register for signal <iDO>.
    Summary:
	inferred  16 D-type flip-flop(s).
Unit <cdiv> synthesized.


Synthesizing Unit <cnop>.
    Related source file is "E:/work/digilentinc/XipHard/cnop.vhd".
    Found 16-bit register for signal <iDO>.
    Summary:
	inferred  16 D-type flip-flop(s).
Unit <cnop> synthesized.


Synthesizing Unit <cadd>.
    Related source file is "E:/work/digilentinc/XipHard/cadd.vhd".
    Found 16-bit register for signal <iDO>.
    Found 16-bit adder for signal <res>.
    Summary:
	inferred  16 D-type flip-flop(s).
	inferred   1 Adder/Subtractor(s).
Unit <cadd> synthesized.


Synthesizing Unit <c2comp>.
    Related source file is "E:/work/digilentinc/XipHard/c2comp.vhd".
    Found 16-bit adder for signal <$n0000> created at line 40.
    Found 16-bit register for signal <iDO>.
    Summary:
	inferred  16 D-type flip-flop(s).
	inferred   1 Adder/Subtractor(s).
Unit <c2comp> synthesized.


Synthesizing Unit <cmul>.
    Related source file is "E:/work/digilentinc/XipHard/cmul.vhd".
WARNING:Xst:647 - Input <MASK<3>> is never used.
    Found 16-bit register for signal <iDO>.
    Summary:
	inferred  16 D-type flip-flop(s).
Unit <cmul> synthesized.


Synthesizing Unit <cbuff>.
    Related source file is "E:/work/digilentinc/XipHard/cbuff.vhd".
    Found 8-bit 4-to-1 multiplexer for signal <DO>.
    Found 11-bit comparator not equal for signal <$n0011> created at line 45.
    Found 11-bit register for signal <iWIDTH>.
    Found 11-bit up counter for signal <rdaddr>.
    Found 2-bit register for signal <rdaddrcs0>.
    Found 11-bit up counter for signal <wraddr>.
    Summary:
	inferred   2 Counter(s).
	inferred  13 D-type flip-flop(s).
	inferred   1 Comparator(s).
	inferred   8 Multiplexer(s).
Unit <cbuff> synthesized.


Synthesizing Unit <creg>.
    Related source file is "E:/work/digilentinc/XipHard/creg.vhd".
    Found 8-bit register for signal <iDO>.
    Summary:
	inferred   8 D-type flip-flop(s).
Unit <creg> synthesized.


Synthesizing Unit <clog>.
    Related source file is "E:/work/digilentinc/XipHard/clog.vhd".
Unit <clog> synthesized.


Synthesizing Unit <conv>.
    Related source file is "E:/work/digilentinc/XipHard/conv.vhd".