📄 pwmeq.vhd
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------------------------------------------------------------------------
-- pwmeq.vhd -- Pulse Width Modulator
------------------------------------------------------------------------
-- Author : Kovacs Laszlo - Attila
------------------------------------------------------------------------
-- Software version: Xilinx ISE 7.1.04i
-- WebPack
------------------------------------------------------------------------
-- This Pulse Width Modulator according to the 4 most significant bits
-- of the data input selects one of the 16 logics (pulse widths).
------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity pwmeq is
Port ( CLK2X : in std_logic;
CLK : in std_logic;
CLK2 : in std_logic;
CLK4 : in std_logic;
DO : out std_logic;
DI : in std_logic_vector(7 downto 0));
end pwmeq;
architecture Behavioral of pwmeq is
begin
with DI(7 downto 4) select
DO <= '1' when "1111", --16
CLK4 or CLK2 or CLK or CLK2X when "1110", --15
CLK4 or CLK2 or CLK when "1101", --14
CLK4 or CLK2 or (CLK and CLK2X) when "1100", --13
CLK4 or CLK2 when "1011", --12
CLK4 or (CLK2 and (CLK or CLK2X)) when "1010", --11
CLK4 or (CLK2 and CLK) when "1001", --10
CLK4 or (CLK2 and CLK and CLK2X) when "1000", --09
CLK4 when "0111", --08
CLK4 and (CLK2 or CLK or CLK2X) when "0110", --07
CLK4 and (CLK2 or CLK) when "0101", --06
CLK4 and (CLK2 or (CLK and CLK2X)) when "0100", --05
CLK4 and CLK2 when "0011", --04
CLK4 and CLK2 and (CLK or CLK2X) when "0010", --03
CLK4 and CLK2 and CLK when "0001", --02
'0' when others;
end Behavioral;
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