graph.vhd

来自「这个是国外大学的项目代码」· VHDL 代码 · 共 20 行

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

library UNISIM;
use UNISIM.VComponents.all;

entity graph is
    Port ( CLK  : in std_logic;
            
end graph;

architecture Behavioral of graph is

begin


end Behavioral;