clog.vhd

来自「这个是国外大学的项目代码」· VHDL 代码 · 共 37 行

------------------------------------------------------------------------
--  clog.vhd -- Pulse Width Modulator
------------------------------------------------------------------------
--  Author : Kovacs Laszlo - Attila 
------------------------------------------------------------------------
-- Software version: Xilinx ISE 7.1.04i
--                   WebPack
------------------------------------------------------------------------
-- This module calculate logarithm.
------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity clog is
    Port ( DI    : in std_logic_vector(7 downto 0);
           DO    : out std_logic_vector(3 downto 0));
end clog;

architecture Behavioral of clog is

begin
    
    DO(3) <= DI(7);
    DO(2 downto 0) <= 
            "000" when DI(6 downto 0) = "0000000" else
            "001" when DI(6 downto 1) = "000000" else
            "010" when DI(6 downto 2) = "00000" else
            "011" when DI(6 downto 3) = "0000" else
            "100" when DI(6 downto 4) = "000" else
            "101" when DI(6 downto 5) = "00" else
            "110";

            
end Behavioral;