cdiv.vhd

来自「这个是国外大学的项目代码」· VHDL 代码 · 共 57 行

------------------------------------------------------------------------
--  cdiv.vhd -- Divider
------------------------------------------------------------------------
--  Author : Kovacs Laszlo - Attila 
------------------------------------------------------------------------
-- Software version: Xilinx ISE 7.1.04i
--                   WebPack
------------------------------------------------------------------------
-- This module performs right shift according to the least significant 
-- 3bits of the MASK. Than the result ('res') is checked whether is 
-- negative or grether than a byte. Than the checked result ('res2') is 
-- negated if the most significant bit of the mask is '1', the divider 
-- was negative.
------------------------------------------------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity cdiv is
    Port ( CLK  : in std_logic;
           EN   : in std_logic;
           MASK : in std_logic_vector(3 downto 0);
           DI   : in std_logic_vector(15 downto 0);
           DO   : out std_logic_vector(15 downto 0));
end cdiv;
architecture Behavioral of cdiv is

signal res : std_logic_vector(15 downto 0) := "0000000000000000";
signal iDO : std_logic_vector(15 downto 0) := "0000000000000000";

begin

    DO <= iDO;
    
    process(CLK)
    begin
        if rising_edge(CLK) and EN = '1' then
            iDO <= res;
        end if;
    end process;
    
    with MASK(2 downto 0) select
    res(14 downto 0) <=
        "000000000000000"       when "000", 
        DI(14 downto 0)         when "001",
        '0'&DI(14 downto 1)     when "010",
        "00"&DI(14 downto 2)    when "011",
        "000"&DI(14 downto 3)   when "100",
        "0000"&DI(14 downto 4)  when "101",
        "00000"&DI(14 downto 5) when others;
    
    res(15) <= DI(15);

end Behavioral;