cadd.syr

这个是国外大学的项目代码

Release 7.1.04i - xst H.42
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.
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--> Reading design: cadd.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
  5) Advanced HDL Synthesis
     5.1) HDL Synthesis Report
  6) Low Level Synthesis
  7) Final Report
     7.1) Device utilization summary
     7.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : "cadd.prj"
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO

---- Target Parameters
Output File Name                   : "cadd"
Output Format                      : NGC
Target Device                      : xc2s200e-6-pq208

---- Source Options
Top Module Name                    : cadd
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Style                          : lut
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
ROM Style                          : Auto
Mux Extraction                     : YES
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
Resource Sharing                   : YES
Multiplier Style                   : lut
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 100
Add Generic Clock Buffer(BUFG)     : 4
Register Duplication               : YES
Equivalent register Removal        : YES
Slice Packing                      : YES
Pack IO Registers into IOBs        : auto

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : NO
Global Optimization                : AllClockNets
RTL Output                         : Yes
Write Timing Constraints           : NO
Hierarchy Separator                : /
Bus Delimiter                      : <>
Case Specifier                     : maintain
Slice Utilization Ratio            : 100
Slice Utilization Ratio Delta      : 5

---- Other Options
lso                                : cadd.lso
Read Cores                         : YES
cross_clock_analysis               : NO
verilog2001                        : YES
safe_implementation                : No
Optimize Instantiated Primitives   : NO
tristate2logic                     : Yes
use_clock_enable                   : Yes
use_sync_set                       : Yes
use_sync_reset                     : Yes
enable_auto_floorplanning          : No

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "E:/work/digilentinc/XipHard/cadd.vhd" in Library work.
Architecture behavioral of Entity cadd is up to date.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <cadd> (Architecture <behavioral>).
Entity <cadd> analyzed. Unit <cadd> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <cadd>.
    Related source file is "E:/work/digilentinc/XipHard/cadd.vhd".
    Found 16-bit register for signal <iDO>.
    Found 16-bit adder for signal <res>.
    Summary:
	inferred  16 D-type flip-flop(s).
	inferred   1 Adder/Subtractor(s).
Unit <cadd> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Advanced Registered AddSub inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Adders/Subtractors               : 1
 16-bit adder                      : 1
# Registers                        : 1
 16-bit register                   : 1

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <cadd> ...
Loading device for application Rf_Device from file '2s200e.nph' in environment C:/Program Files/Xilinx.

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block cadd, actual ratio is 0.

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : cadd.ngr
Top Level Output File Name         : cadd
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 50

Macro Statistics :
# Registers                        : 1
#      16-bit register             : 1
# Adders/Subtractors               : 1
#      16-bit adder                : 1

Cell Usage :
# BELS                             : 47
#      GND                         : 1
#      LUT2                        : 16
#      MUXCY                       : 15
#      XORCY                       : 15
# FlipFlops/Latches                : 16
#      FDE                         : 16
# Clock Buffers                    : 1
#      BUFGP                       : 1
# IO Buffers                       : 49
#      IBUF                        : 33
#      OBUF                        : 16
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 2s200epq208-6 

 Number of Slices:                       8  out of   2352     0%  
 Number of Slice Flip Flops:            16  out of   4704     0%  
 Number of 4 input LUTs:                16  out of   4704     0%  
 Number of bonded IOBs:                 50  out of    146    34%  
 Number of GCLKs:                        1  out of      4    25%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
CLK                                | BUFGP                  | 16    |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -6

   Minimum period: No path found
   Minimum input arrival time before clock: 4.884ns
   Maximum output required time after clock: 6.514ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'CLK'
  Total number of paths / destination ports: 408 / 32
-------------------------------------------------------------------------
Offset:              4.884ns (Levels of Logic = 18)
  Source:            DI0<0> (PAD)
  Destination:       iDO_15 (FF)
  Destination Clock: CLK rising

  Data Path: DI0<0> to iDO_15
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             1   0.797   0.920  DI0_0_IBUF (DI0_0_IBUF)
     LUT2:I0->O            2   0.468   0.000  cadd_res<0>lut (res<0>)
     MUXCY:S->O            1   0.515   0.000  cadd_res<0>cy (cadd_res<0>_cyo)
     MUXCY:CI->O           1   0.058   0.000  cadd_res<1>cy (cadd_res<1>_cyo)
     MUXCY:CI->O           1   0.058   0.000  cadd_res<2>cy (cadd_res<2>_cyo)
     MUXCY:CI->O           1   0.058   0.000  cadd_res<3>cy (cadd_res<3>_cyo)
     MUXCY:CI->O           1   0.058   0.000  cadd_res<4>cy (cadd_res<4>_cyo)
     MUXCY:CI->O           1   0.058   0.000  cadd_res<5>cy (cadd_res<5>_cyo)
     MUXCY:CI->O           1   0.058   0.000  cadd_res<6>cy (cadd_res<6>_cyo)
     MUXCY:CI->O           1   0.058   0.000  cadd_res<7>cy (cadd_res<7>_cyo)
     MUXCY:CI->O           1   0.058   0.000  cadd_res<8>cy (cadd_res<8>_cyo)
     MUXCY:CI->O           1   0.058   0.000  cadd_res<9>cy (cadd_res<9>_cyo)
     MUXCY:CI->O           1   0.058   0.000  cadd_res<10>cy (cadd_res<10>_cyo)
     MUXCY:CI->O           1   0.058   0.000  cadd_res<11>cy (cadd_res<11>_cyo)
     MUXCY:CI->O           1   0.058   0.000  cadd_res<12>cy (cadd_res<12>_cyo)
     MUXCY:CI->O           1   0.058   0.000  cadd_res<13>cy (cadd_res<13>_cyo)
     MUXCY:CI->O           0   0.058   0.000  cadd_res<14>cy (cadd_res<14>_cyo)
     XORCY:CI->O           1   0.648   0.000  cadd_res<15>_xor (res<15>)
     FDE:D                     0.724          iDO_15
    ----------------------------------------
    Total                      4.884ns (3.964ns logic, 0.920ns route)
                                       (81.2% logic, 18.8% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'CLK'
  Total number of paths / destination ports: 16 / 16
-------------------------------------------------------------------------
Offset:              6.514ns (Levels of Logic = 1)
  Source:            iDO_15 (FF)
  Destination:       DO<15> (PAD)
  Source Clock:      CLK rising

  Data Path: iDO_15 to DO<15>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDE:C->Q              1   0.992   0.920  iDO_15 (iDO_15)
     OBUF:I->O                 4.602          DO_15_OBUF (DO<15>)
    ----------------------------------------
    Total                      6.514ns (5.594ns logic, 0.920ns route)
                                       (85.9% logic, 14.1% route)

=========================================================================
CPU : 4.77 / 5.19 s | Elapsed : 5.00 / 5.00 s
 
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Total memory usage is 88776 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :    0 (   0 filtered)
Number of infos    :    0 (   0 filtered)