📄 conv.vhd
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------------------------------------------------------------------------
-- conv.vhd -- Convolution Array
------------------------------------------------------------------------
-- Author : Kovacs Laszlo - Attila
------------------------------------------------------------------------
-- Software version: Xilinx ISE 7.1.04i
-- WebPack
------------------------------------------------------------------------
-- This module is the image processing array.
------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity conv is
Port ( CLK : in std_logic;
MASK0 : in std_logic_vector(7 downto 0);
MASK1 : in std_logic_vector(7 downto 0);
MASK2 : in std_logic_vector(7 downto 0);
MASK3 : in std_logic_vector(7 downto 0);
MASK4 : in std_logic_vector(7 downto 0);
MASK5 : in std_logic_vector(7 downto 0);
MASK6 : in std_logic_vector(7 downto 0);
MASK7 : in std_logic_vector(7 downto 0);
MASK8 : in std_logic_vector(7 downto 0);
MASK9 : in std_logic_vector(7 downto 0);
IMGW : in std_logic_vector(10 downto 0);
MEN : in std_logic;
MVIN : in std_logic;
MVOUT : out std_logic;
FLINE : in std_logic;
LLINE : in std_logic;
MDI : in std_logic_vector(7 downto 0);
MDO : out std_logic_vector(7 downto 0));
end conv;
architecture Behavioral of conv is
component clog is
Port ( DI : in std_logic_vector(7 downto 0);
DO : out std_logic_vector(3 downto 0));
end component;
component creg is
Port ( CLK : in std_logic;
EN : in std_logic;
DI : in std_logic_vector(7 downto 0);
DO : out std_logic_vector(7 downto 0));
end component;
component cbuff is
Port ( CLK : in std_logic;
EN : in std_logic;
DI : in std_logic_vector(7 downto 0);
DO : out std_logic_vector(7 downto 0);
WIDTH : in std_logic_vector(10 downto 0));
end component;
component cnop is
Port ( CLK : in std_logic;
EN : in std_logic;
DI : in std_logic_vector(15 downto 0);
DO : out std_logic_vector(15 downto 0));
end component;
component cmul is
Port ( CLK : in std_logic;
EN : in std_logic;
MASK : in std_logic_vector(3 downto 0);
DI : in std_logic_vector(7 downto 0);
DO : out std_logic_vector(15 downto 0));
end component;
component cadd is
Port ( CLK : in std_logic;
EN : in std_logic;
DI0 : in std_logic_vector(15 downto 0);
DI1 : in std_logic_vector(15 downto 0);
DO : out std_logic_vector(15 downto 0));
end component;
component cdiv is
Port ( CLK : in std_logic;
EN : in std_logic;
MASK : in std_logic_vector(3 downto 0);
DI : in std_logic_vector(15 downto 0);
DO : out std_logic_vector(15 downto 0));
end component;
component cround is
Port ( CLK : in std_logic;
EN : in std_logic;
MASK : in std_logic;
DI : in std_logic_vector(15 downto 0);
DO : out std_logic_vector(7 downto 0));
end component;
component c2comp is
Port ( CLK : in std_logic;
EN : in std_logic;
MASK : in std_logic;
DI : in std_logic_vector(15 downto 0);
DO : out std_logic_vector(15 downto 0));
end component;
signal w11,w12,w13,w21,w22,w23,w31,w32,w33,l1,l2,l3
: std_logic_vector(7 downto 0) := "00000000";
signal m0,m1,m2,m3,m4,m5,m6,m7,m8,c0,c1,c2,c3,c4,c5,c6,c7,c8,
m8a,m01,m23,m45,m67,m8b,m03,m47,m8c,m07,m08, mdiv
: std_logic_vector(15 downto 0) := "0000000000000000";
signal msk0,msk1,msk2,msk3,msk4,msk5,msk6,msk7,msk8,msk9
: std_logic_vector(3 downto 0) := "0000";
signal valid : std_logic_vector(11 downto 0) := "000000000000";
begin
MVOUT <= valid(11);
process(CLK)
begin
if rising_edge(CLK) and MEN = '1' then
valid <= valid(10 downto 0) & MVIN;
end if;
end process;
l1 <= w21 when LLINE = '1' else w11;
l2 <= w11 when FLINE = '1' else w21;
l3 <= w11 when FLINE = '1' else w31;
log0:clog port map(MASK0,msk0);
log1:clog port map(MASK1,msk1);
log2:clog port map(MASK2,msk2);
log3:clog port map(MASK3,msk3);
log4:clog port map(MASK4,msk4);
log5:clog port map(MASK5,msk5);
log6:clog port map(MASK6,msk6);
log7:clog port map(MASK7,msk7);
log8:clog port map(MASK8,msk8);
log9:clog port map(MASK9,msk9);
reg11:creg port map(CLK,MEN,MDI,w11);
reg12:creg port map(CLK,MEN,l1,w12);
reg13:creg port map(CLK,MEN,w12,w13);
buffa:cbuff port map(CLK,MEN,w13,w21,IMGW);
reg22:creg port map(CLK,MEN,l2,w22);
reg23:creg port map(CLK,MEN,w22,w23);
buffb:cbuff port map(CLK,MEN,w23,w31,IMGW);
reg32:creg port map(CLK,MEN,l3,w32);
reg33:creg port map(CLK,MEN,w32,w33);
mul0:cmul port map(CLK,MEN,msk0,w11,m0);
mul1:cmul port map(CLK,MEN,msk1,w12,m1);
mul2:cmul port map(CLK,MEN,msk2,w13,m2);
mul3:cmul port map(CLK,MEN,msk3,w21,m3);
mul4:cmul port map(CLK,MEN,msk4,w22,m4);
mul5:cmul port map(CLK,MEN,msk5,w23,m5);
mul6:cmul port map(CLK,MEN,msk6,w31,m6);
mul7:cmul port map(CLK,MEN,msk7,w32,m7);
mul8:cmul port map(CLK,MEN,msk8,w33,m8);
comp0:c2comp port map(CLK,MEN,msk0(3),m0,c0);
comp1:c2comp port map(CLK,MEN,msk1(3),m1,c1);
comp2:c2comp port map(CLK,MEN,msk2(3),m2,c2);
comp3:c2comp port map(CLK,MEN,msk3(3),m3,c3);
comp4:c2comp port map(CLK,MEN,msk4(3),m4,c4);
comp5:c2comp port map(CLK,MEN,msk5(3),m5,c5);
comp6:c2comp port map(CLK,MEN,msk6(3),m6,c6);
comp7:c2comp port map(CLK,MEN,msk7(3),m7,c7);
comp8:c2comp port map(CLK,MEN,msk8(3),m8,c8);
add01:cadd port map(CLK,MEN,c0,c1,m01);
add23:cadd port map(CLK,MEN,c2,c3,m23);
add45:cadd port map(CLK,MEN,c4,c5,m45);
add67:cadd port map(CLK,MEN,c6,c7,m67);
nop8a:cnop port map(CLK,MEN,c8,m8a);
add03:cadd port map(CLK,MEN,m01,m23,m03);
add47:cadd port map(CLK,MEN,m45,m67,m47);
nop8b:cnop port map(CLK,MEN,m8a,m8b);
add07:cadd port map(CLK,MEN,m03,m47,m07);
nop8c:cnop port map(CLK,MEN,m8b,m8c);
add08:cadd port map(CLK,MEN,m07,m8c,m08);
div08:cdiv port map(CLK,MEN,msk9,m08,mdiv);
round0:cround port map(CLK,MEN,msk9(3),mdiv,MDO);
end Behavioral;
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