clkgen.vhd

来自「这个是国外大学的项目代码」· VHDL 代码 · 共 82 行

------------------------------------------------------------------------
--  clkgen.vhd -- Clock generator 
------------------------------------------------------------------------
--  Author : Kovacs Laszlo - Attila 
------------------------------------------------------------------------
-- Software version: Xilinx ISE 7.1.04i
--                   WebPack
------------------------------------------------------------------------
-- The clkgen module generates the clock signals for the PWM. 
-- Multiplied and locked clk2x with CLKDLLE, clk2, clk4 and clk8.
------------------------------------------------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
library UNISIM;
use UNISIM.VComponents.all;

entity clkgen is
    Port ( CLK   : in std_logic;
           CLK2X : out std_logic;
           CLK2  : out std_logic;
           CLK4  : out std_logic;
           CLK8  : out std_logic);
end clkgen;
architecture Behavioral of clkgen is

signal iCLK, iCLK2X, iCLK2, iCLK4, iCLK8 : std_logic := '0';
signal clkin, clk2xdll : std_logic := '0';

begin
    CLK2X <= iCLK2x;
    CLK2 <= iCLK2;
    CLK4 <= iCLK4;
    CLK8 <= iCLK8;
    
clkdlle1 : CLKDLLE 
   port map (
      CLK0 => open,
      CLK180 => open,
      CLK270 => open,
      CLK2X => clk2xdll,
      CLK90 => open,
      CLKDV => open,  
      LOCKED => open,
      CLKFB => iCLK2X,  
      CLKIN => CLK,  
      RST => '0');

clkinbuf : BUFG    
    port map (
        I => CLK, 
        O => clkin);
clk2xbuf : BUFG    
    port map (
        I => clk2xdll, 
        O => iCLK2X);

    process(CLK)
    begin
        if rising_edge(CLK) then
            iCLK2 <= not iCLK2;
        end if;
    end process;

    process(iCLK2)
    begin
        if rising_edge(iCLK2) then
            iCLK4 <= not iCLK4;
        end if;
    end process;

    process(iCLK4)
    begin
        if rising_edge(iCLK4) then
            iCLK8 <= not iCLK8;
        end if;
    end process;

end Behavioral;