img.syr

这个是国外大学的项目代码

Release 7.1.04i - xst H.42
Copyright (c) 1995-2005 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to __projnav
CPU : 0.00 / 0.34 s | Elapsed : 0.00 / 1.00 s
 
--> Parameter xsthdpdir set to ./xst
CPU : 0.00 / 0.34 s | Elapsed : 0.00 / 1.00 s
 
--> Reading design: img.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
  5) Advanced HDL Synthesis
     5.1) HDL Synthesis Report
  6) Low Level Synthesis
  7) Final Report
     7.1) Device utilization summary
     7.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : "img.prj"
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO

---- Target Parameters
Output File Name                   : "img"
Output Format                      : NGC
Target Device                      : xc2s200e-6-pq208

---- Source Options
Top Module Name                    : img
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Style                          : lut
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
ROM Style                          : Auto
Mux Extraction                     : YES
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
Resource Sharing                   : YES
Multiplier Style                   : lut
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 100
Add Generic Clock Buffer(BUFG)     : 4
Register Duplication               : YES
Equivalent register Removal        : YES
Slice Packing                      : YES
Pack IO Registers into IOBs        : auto

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : NO
Global Optimization                : AllClockNets
RTL Output                         : Yes
Write Timing Constraints           : NO
Hierarchy Separator                : /
Bus Delimiter                      : <>
Case Specifier                     : maintain
Slice Utilization Ratio            : 100
Slice Utilization Ratio Delta      : 5

---- Other Options
lso                                : img.lso
Read Cores                         : YES
cross_clock_analysis               : NO
verilog2001                        : YES
safe_implementation                : No
Optimize Instantiated Primitives   : NO
tristate2logic                     : Yes
use_clock_enable                   : Yes
use_sync_set                       : Yes
use_sync_reset                     : Yes
enable_auto_floorplanning          : No

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "E:/work/digilentinc/XipHard/pwmmd.vhd" in Library work.
Architecture behavioral of Entity pwmmd is up to date.
Compiling vhdl file "E:/work/digilentinc/XipHard/pwmeq.vhd" in Library work.
Architecture behavioral of Entity pwmeq is up to date.
Compiling vhdl file "E:/work/digilentinc/XipHard/pwmhi.vhd" in Library work.
Architecture behavioral of Entity pwmhi is up to date.
Compiling vhdl file "E:/work/digilentinc/XipHard/pwmlo.vhd" in Library work.
Architecture behavioral of Entity pwmlo is up to date.
Compiling vhdl file "E:/work/digilentinc/XipHard/pwm2x.vhd" in Library work.
Architecture behavioral of Entity pwm2x is up to date.
Compiling vhdl file "E:/work/digilentinc/XipHard/pwminv2x.vhd" in Library work.
Architecture behavioral of Entity pwminv2x is up to date.
Compiling vhdl file "E:/work/digilentinc/XipHard/pwm2xeq.vhd" in Library work.
Architecture behavioral of Entity pwm2xeq is up to date.
Compiling vhdl file "E:/work/digilentinc/XipHard/vga.vhd" in Library work.
Architecture behavioral of Entity vga is up to date.
Compiling vhdl file "E:/work/digilentinc/XipHard/clkgen.vhd" in Library work.
Architecture behavioral of Entity clkgen is up to date.
Compiling vhdl file "E:/work/digilentinc/XipHard/pixel.vhd" in Library work.
Architecture behavioral of Entity pixel is up to date.
Compiling vhdl file "E:/work/digilentinc/XipHard/img.vhd" in Library work.
Entity <img> compiled.
Entity <img> (Architecture <behavioral>) compiled.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <img> (Architecture <behavioral>).
Entity <img> analyzed. Unit <img> generated.

Analyzing Entity <vga> (Architecture <behavioral>).
Entity <vga> analyzed. Unit <vga> generated.

Analyzing Entity <clkgen> (Architecture <behavioral>).
Entity <clkgen> analyzed. Unit <clkgen> generated.

Analyzing Entity <pixel> (Architecture <behavioral>).
Entity <pixel> analyzed. Unit <pixel> generated.

Analyzing Entity <pwmmd> (Architecture <behavioral>).
Entity <pwmmd> analyzed. Unit <pwmmd> generated.

Analyzing Entity <pwmeq> (Architecture <behavioral>).
Entity <pwmeq> analyzed. Unit <pwmeq> generated.

Analyzing Entity <pwmhi> (Architecture <behavioral>).
Entity <pwmhi> analyzed. Unit <pwmhi> generated.

Analyzing Entity <pwmlo> (Architecture <behavioral>).
Entity <pwmlo> analyzed. Unit <pwmlo> generated.

Analyzing Entity <pwm2x> (Architecture <behavioral>).
Entity <pwm2x> analyzed. Unit <pwm2x> generated.

Analyzing Entity <pwminv2x> (Architecture <behavioral>).
Entity <pwminv2x> analyzed. Unit <pwminv2x> generated.

Analyzing Entity <pwm2xeq> (Architecture <behavioral>).
Entity <pwm2xeq> analyzed. Unit <pwm2xeq> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <pwm2xeq>.
    Related source file is "E:/work/digilentinc/XipHard/pwm2xeq.vhd".
WARNING:Xst:647 - Input <DI<3:0>> is never used.
    Found 1-bit 16-to-1 multiplexer for signal <DO>.
    Summary:
	inferred   1 Multiplexer(s).
Unit <pwm2xeq> synthesized.


Synthesizing Unit <pwminv2x>.
    Related source file is "E:/work/digilentinc/XipHard/pwminv2x.vhd".
WARNING:Xst:647 - Input <DI<2:0>> is never used.
    Found 1-bit 32-to-1 multiplexer for signal <DO>.
    Summary:
	inferred   1 Multiplexer(s).
Unit <pwminv2x> synthesized.


Synthesizing Unit <pwm2x>.
    Related source file is "E:/work/digilentinc/XipHard/pwm2x.vhd".
WARNING:Xst:647 - Input <DI<2:0>> is never used.
    Found 1-bit 32-to-1 multiplexer for signal <DO>.
    Summary:
	inferred   1 Multiplexer(s).
Unit <pwm2x> synthesized.


Synthesizing Unit <pwmlo>.
    Related source file is "E:/work/digilentinc/XipHard/pwmlo.vhd".
WARNING:Xst:647 - Input <DI<2:0>> is never used.
    Found 1-bit 32-to-1 multiplexer for signal <DO>.
    Summary:
	inferred   1 Multiplexer(s).
Unit <pwmlo> synthesized.


Synthesizing Unit <pwmhi>.
    Related source file is "E:/work/digilentinc/XipHard/pwmhi.vhd".
WARNING:Xst:647 - Input <DI<2:0>> is never used.
Unit <pwmhi> synthesized.


Synthesizing Unit <pwmeq>.
    Related source file is "E:/work/digilentinc/XipHard/pwmeq.vhd".
WARNING:Xst:647 - Input <DI<3:0>> is never used.
    Found 1-bit 16-to-1 multiplexer for signal <DO>.
    Summary:
	inferred   1 Multiplexer(s).
Unit <pwmeq> synthesized.


Synthesizing Unit <pwmmd>.
    Related source file is "E:/work/digilentinc/XipHard/pwmmd.vhd".
WARNING:Xst:647 - Input <DI<2:0>> is never used.
Unit <pwmmd> synthesized.


Synthesizing Unit <pixel>.
    Related source file is "E:/work/digilentinc/XipHard/pixel.vhd".
    Found 1-bit 8-to-1 multiplexer for signal <GRN>.
    Found 1-bit 8-to-1 multiplexer for signal <RED>.
    Found 1-bit 8-to-1 multiplexer for signal <BLU>.
    Summary:
	inferred   3 Multiplexer(s).
Unit <pixel> synthesized.


Synthesizing Unit <clkgen>.
    Related source file is "E:/work/digilentinc/XipHard/clkgen.vhd".
WARNING:Xst:646 - Signal <clkin> is assigned but never used.
WARNING:Xst:1780 - Signal <iCLK> is never used or assigned.
    Found 1-bit register for signal <iCLK2>.
    Found 1-bit register for signal <iCLK4>.
    Found 1-bit register for signal <iCLK8>.
    Summary:
	inferred   3 D-type flip-flop(s).
Unit <clkgen> synthesized.


Synthesizing Unit <vga>.
    Related source file is "E:/work/digilentinc/XipHard/vga.vhd".
    Found 11-bit adder for signal <$n0004> created at line 66.
    Found 11-bit comparator equal for signal <$n0010> created at line 98.
    Found 11-bit comparator greatequal for signal <$n0011> created at line 59.
    Found 11-bit comparator less for signal <$n0012> created at line 59.
    Found 10-bit comparator greatequal for signal <$n0013> created at line 60.
    Found 10-bit comparator less for signal <$n0014> created at line 60.
    Found 11-bit comparator less for signal <$n0015> created at line 61.
    Found 10-bit comparator less for signal <$n0016> created at line 61.
    Found 11-bit adder for signal <hcount0>.
    Found 11-bit up counter for signal <ihc>.
    Found 28-bit up counter for signal <initvga>.
    Found 10-bit up counter for signal <ivc>.
    Summary:
	inferred   3 Counter(s).
	inferred   2 Adder/Subtractor(s).
	inferred   7 Comparator(s).
Unit <vga> synthesized.


Synthesizing Unit <img>.
    Related source file is "E:/work/digilentinc/XipHard/img.vhd".
WARNING:Xst:647 - Input <SWT<4:0>> is never used.
    Found 20-bit register for signal <IADR>.
    Found 8-bit 8-to-1 multiplexer for signal <$n0012>.
    Found 8-bit 8-to-1 multiplexer for signal <$n0014>.
    Found 8-bit 8-to-1 multiplexer for signal <$n0015>.
    Found 10-bit comparator less for signal <$n0028> created at line 100.
    Found 11-bit comparator less for signal <$n0029> created at line 100.
    Found 10-bit comparator less for signal <$n0030> created at line 98.
    Found 11-bit comparator less for signal <$n0031> created at line 98.
    Found 8-bit register for signal <dblu>.
    Found 8-bit register for signal <dgrn>.
    Found 8-bit register for signal <dred>.
    Found 20-bit up counter for signal <eadr>.
    Found 8-bit register for signal <eblu>.
    Found 8-bit register for signal <egrn>.
    Found 8-bit register for signal <ered>.
    Found 20-bit up counter for signal <oadr>.
    Found 8-bit register for signal <oblu>.
    Found 8-bit register for signal <ogrn>.
    Found 8-bit register for signal <ored>.
    Summary:
	inferred   2 Counter(s).
	inferred  92 D-type flip-flop(s).
	inferred   4 Comparator(s).
	inferred  24 Multiplexer(s).
Unit <img> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Advanced Registered AddSub inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Adders/Subtractors               : 2
 11-bit adder                      : 2
# Counters                         : 5
 10-bit up counter                 : 1
 11-bit up counter                 : 1
 20-bit up counter                 : 2
 28-bit up counter                 : 1
# Registers                        : 13
 1-bit register                    : 3
 20-bit register                   : 1
 8-bit register                    : 9
# Comparators                      : 11
 10-bit comparator greatequal      : 1
 10-bit comparator less            : 4
 11-bit comparator equal           : 1
 11-bit comparator greatequal      : 1
 11-bit comparator less            : 4
# Multiplexers                     : 21
 1-bit 16-to-1 multiplexer         : 6
 1-bit 32-to-1 multiplexer         : 9
 1-bit 8-to-1 multiplexer          : 3
 8-bit 8-to-1 multiplexer          : 3

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <img> ...