串入并出1-5.txt

来自「本压缩包含有一个窜入并出的程序」· 文本 代码 · 共 30 行

library ieee;
use ieee.std_logic_1164.all;
entity shifter is
port(shift :in std_logic;
          y:out  std_logic_vector(4 downto 0);
        clk:in std_logic);
end shifter;
architecture bhv of shifter is
signal d:std_logic_vector(4 downto 0);
begin 
process(clk)
variable   cont: integer range 0 to 5 ;

begin
if clk'event and clk='1' then 
 if cont=5 then y<=d;d <="00000";cont:=0;
else cont:=cont+1;
case cont is 
when 1=>d(4)<=shift;
when 2=>d(3)<=shift;           
when 3=>d(2)<=shift;
when 4=>d(1)<=shift;
when 5=>d(0)<=shift;
when others=>null;
end case;
end if;
end if;
end process;
end bhv;