maxmin.map.rpt

一个自己编写的这次2008北京市电子竞赛VHDL源程序

Analysis & Synthesis report for maxmin
Wed May 21 14:30:25 2008
Version 5.1 Build 176 10/26/2005 SJ Full Version


---------------------
; Table of Contents ;
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  1. Legal Notice
  2. Analysis & Synthesis Summary
  3. Analysis & Synthesis Settings
  4. Analysis & Synthesis Source Files Read
  5. Analysis & Synthesis Resource Usage Summary
  6. Analysis & Synthesis Resource Utilization by Entity
  7. State Machine - |maxmin|ADC0820:inst|fsm3
  8. State Machine - |maxmin|ADC0820:inst|current_state
  9. User-Specified and Inferred Latches
 10. General Register Statistics
 11. Parameter Settings for Inferred Entity Instance: display1:inst3|lpm_mult:mult_rtl_0
 12. Parameter Settings for Inferred Entity Instance: display1:inst3|lpm_divide:div_rtl_1
 13. Parameter Settings for Inferred Entity Instance: display1:inst3|lpm_divide:div_rtl_2
 14. Parameter Settings for Inferred Entity Instance: display1:inst3|lpm_mult:mult_rtl_3
 15. Parameter Settings for Inferred Entity Instance: display1:inst3|lpm_divide:div_rtl_4
 16. Parameter Settings for Inferred Entity Instance: display1:inst3|lpm_divide:div_rtl_5
 17. Parameter Settings for Inferred Entity Instance: display1:inst3|lpm_mult:mult_rtl_6
 18. Parameter Settings for Inferred Entity Instance: display1:inst3|lpm_divide:div_rtl_7
 19. Parameter Settings for Inferred Entity Instance: display1:inst3|lpm_divide:div_rtl_8
 20. lpm_mult Parameter Settings by Entity Instance
 21. Analysis & Synthesis Equations
 22. Analysis & Synthesis Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2005 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic 
functions, and any output files any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Altera Program License 
Subscription Agreement, Altera MegaCore Function License 
Agreement, or other applicable license agreement, including, 
without limitation, that your use is for the sole purpose of 
programming logic devices manufactured by Altera and sold by 
Altera or its authorized distributors.  Please refer to the 
applicable agreement for further details.



+------------------------------------------------------------------------+
; Analysis & Synthesis Summary                                           ;
+-----------------------------+------------------------------------------+
; Analysis & Synthesis Status ; Successful - Wed May 21 14:30:25 2008    ;
; Quartus II Version          ; 5.1 Build 176 10/26/2005 SJ Full Version ;
; Revision Name               ; maxmin                                   ;
; Top-level Entity Name       ; maxmin                                   ;
; Family                      ; Cyclone                                  ;
; Total logic elements        ; 759                                      ;
; Total pins                  ; 37                                       ;
; Total virtual pins          ; 0                                        ;
; Total memory bits           ; 0                                        ;
; Total PLLs                  ; 0                                        ;
+-----------------------------+------------------------------------------+


+--------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings                                                                                ;
+--------------------------------------------------------------------+--------------------+--------------------+
; Option                                                             ; Setting            ; Default Value      ;
+--------------------------------------------------------------------+--------------------+--------------------+
; Device                                                             ; EP1C3T144C8        ;                    ;
; Top-level entity name                                              ; maxmin             ; maxmin             ;
; Family name                                                        ; Cyclone            ; Stratix            ;
; Use smart compilation                                              ; Off                ; Off                ;
; Restructure Multiplexers                                           ; Auto               ; Auto               ;
; Create Debugging Nodes for IP Cores                                ; Off                ; Off                ;
; Preserve fewer node names                                          ; On                 ; On                 ;
; Disable OpenCore Plus hardware evaluation                          ; Off                ; Off                ;
; Verilog Version                                                    ; Verilog_2001       ; Verilog_2001       ;
; VHDL Version                                                       ; VHDL93             ; VHDL93             ;
; State Machine Processing                                           ; Auto               ; Auto               ;
; Extract Verilog State Machines                                     ; On                 ; On                 ;
; Extract VHDL State Machines                                        ; On                 ; On                 ;
; Add Pass-Through Logic to Inferred RAMs                            ; On                 ; On                 ;
; NOT Gate Push-Back                                                 ; On                 ; On                 ;
; Power-Up Don't Care                                                ; On                 ; On                 ;
; Remove Redundant Logic Cells                                       ; Off                ; Off                ;
; Remove Duplicate Registers                                         ; On                 ; On                 ;
; Ignore CARRY Buffers                                               ; Off                ; Off                ;
; Ignore CASCADE Buffers                                             ; Off                ; Off                ;
; Ignore GLOBAL Buffers                                              ; Off                ; Off                ;
; Ignore ROW GLOBAL Buffers                                          ; Off                ; Off                ;
; Ignore LCELL Buffers                                               ; Off                ; Off                ;
; Ignore SOFT Buffers                                                ; On                 ; On                 ;