maxmin.tan.qmsg

一个自己编写的这次2008北京市电子竞赛VHDL源程序

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "maxmin.bdf" "" { Schematic "E:/Electronic Competition/maxmin/maxmin.bdf" { { 224 -8 160 240 "clk" "" } } } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "5 " "Warning: Found 5 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "ADC0820:inst\|lock " "Info: Detected ripple clock \"ADC0820:inst\|lock\" as buffer" {  } { { "ADC0820.vhd" "" { Text "E:/Electronic Competition/maxmin/ADC0820.vhd" 24 -1 0 } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "ADC0820:inst\|lock" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "ADC0820:inst\|current_state.st2 " "Info: Detected ripple clock \"ADC0820:inst\|current_state.st2\" as buffer" {  } { { "ADC0820.vhd" "" { Text "E:/Electronic Competition/maxmin/ADC0820.vhd" 50 -1 0 } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "ADC0820:inst\|current_state.st2" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "ADC0820:inst\|clko " "Info: Detected ripple clock \"ADC0820:inst\|clko\" as buffer" {  } { { "ADC0820.vhd" "" { Text "E:/Electronic Competition/maxmin/ADC0820.vhd" 20 -1 0 } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "ADC0820:inst\|clko" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "calculate:inst2\|clko " "Info: Detected ripple clock \"calculate:inst2\|clko\" as buffer" {  } { { "calculate.vhd" "" { Text "E:/Electronic Competition/maxmin/calculate.vhd" 77 -1 0 } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "calculate:inst2\|clko" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "ADC0820:inst\|current_state.st0 " "Info: Detected ripple clock \"ADC0820:inst\|current_state.st0\" as buffer" {  } { { "ADC0820.vhd" "" { Text "E:/Electronic Competition/maxmin/ADC0820.vhd" 50 -1 0 } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "ADC0820:inst\|current_state.st0" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}