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📄 maxmin.map.qmsg

📁 一个自己编写的这次2008北京市电子竞赛VHDL源程序
💻 QMSG
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{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus51/libraries/megafunctions/lpm_mult.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus51/libraries/megafunctions/lpm_mult.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_mult " "Info: Found entity 1: lpm_mult" {  } { { "lpm_mult.tdf" "" { Text "c:/altera/quartus51/libraries/megafunctions/lpm_mult.tdf" 281 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus51/libraries/megafunctions/multcore.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus51/libraries/megafunctions/multcore.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 multcore " "Info: Found entity 1: multcore" {  } { { "multcore.tdf" "" { Text "c:/altera/quartus51/libraries/megafunctions/multcore.tdf" 175 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus51/libraries/megafunctions/mpar_add.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus51/libraries/megafunctions/mpar_add.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 mpar_add " "Info: Found entity 1: mpar_add" {  } { { "mpar_add.tdf" "" { Text "c:/altera/quartus51/libraries/megafunctions/mpar_add.tdf" 60 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus51/libraries/megafunctions/lpm_add_sub.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus51/libraries/megafunctions/lpm_add_sub.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_add_sub " "Info: Found entity 1: lpm_add_sub" {  } { { "lpm_add_sub.tdf" "" { Text "c:/altera/quartus51/libraries/megafunctions/lpm_add_sub.tdf" 100 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus51/libraries/megafunctions/addcore.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus51/libraries/megafunctions/addcore.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 addcore " "Info: Found entity 1: addcore" {  } { { "addcore.tdf" "" { Text "c:/altera/quartus51/libraries/megafunctions/addcore.tdf" 73 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus51/libraries/megafunctions/a_csnbuffer.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus51/libraries/megafunctions/a_csnbuffer.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 a_csnbuffer " "Info: Found entity 1: a_csnbuffer" {  } { { "a_csnbuffer.tdf" "" { Text "c:/altera/quartus51/libraries/megafunctions/a_csnbuffer.tdf" 10 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus51/libraries/megafunctions/altshift.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus51/libraries/megafunctions/altshift.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altshift " "Info: Found entity 1: altshift" {  } { { "altshift.tdf" "" { Text "c:/altera/quartus51/libraries/megafunctions/altshift.tdf" 28 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus51/libraries/megafunctions/lpm_divide.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus51/libraries/megafunctions/lpm_divide.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_divide " "Info: Found entity 1: lpm_divide" {  } { { "lpm_divide.tdf" "" { Text "c:/altera/quartus51/libraries/megafunctions/lpm_divide.tdf" 116 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/lpm_divide_5nf.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/lpm_divide_5nf.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_divide_5nf " "Info: Found entity 1: lpm_divide_5nf" {  } { { "db/lpm_divide_5nf.tdf" "" { Text "E:/Electronic Competition/maxmin/db/lpm_divide_5nf.tdf" 24 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/sign_div_unsign_7jg.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/sign_div_unsign_7jg.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 sign_div_unsign_7jg " "Info: Found entity 1: sign_div_unsign_7jg" {  } { { "db/sign_div_unsign_7jg.tdf" "" { Text "E:/Electronic Competition/maxmin/db/sign_div_unsign_7jg.tdf" 26 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/alt_u_div_jod.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/alt_u_div_jod.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 alt_u_div_jod " "Info: Found entity 1: alt_u_div_jod" {  } { { "db/alt_u_div_jod.tdf" "" { Text "E:/Electronic Competition/maxmin/db/alt_u_div_jod.tdf" 40 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_ke8.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/add_sub_ke8.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_ke8 " "Info: Found entity 1: add_sub_ke8" {  } { { "db/add_sub_ke8.tdf" "" { Text "E:/Electronic Competition/maxmin/db/add_sub_ke8.tdf" 22 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_le8.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/add_sub_le8.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_le8 " "Info: Found entity 1: add_sub_le8" {  } { { "db/add_sub_le8.tdf" "" { Text "E:/Electronic Competition/maxmin/db/add_sub_le8.tdf" 22 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_se8.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/add_sub_se8.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_se8 " "Info: Found entity 1: add_sub_se8" {  } { { "db/add_sub_se8.tdf" "" { Text "E:/Electronic Competition/maxmin/db/add_sub_se8.tdf" 24 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_me8.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/add_sub_me8.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_me8 " "Info: Found entity 1: add_sub_me8" {  } { { "db/add_sub_me8.tdf" "" { Text "E:/Electronic Competition/maxmin/db/add_sub_me8.tdf" 24 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_ne8.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/add_sub_ne8.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_ne8 " "Info: Found entity 1: add_sub_ne8" {  } { { "db/add_sub_ne8.tdf" "" { Text "E:/Electronic Competition/maxmin/db/add_sub_ne8.tdf" 24 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_oe8.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/add_sub_oe8.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_oe8 " "Info: Found entity 1: add_sub_oe8" {  } { { "db/add_sub_oe8.tdf" "" { Text "E:/Electronic Competition/maxmin/db/add_sub_oe8.tdf" 24 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_pe8.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/add_sub_pe8.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_pe8 " "Info: Found entity 1: add_sub_pe8" {  } { { "db/add_sub_pe8.tdf" "" { Text "E:/Electronic Competition/maxmin/db/add_sub_pe8.tdf" 24 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_qe8.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/add_sub_qe8.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_qe8 " "Info: Found entity 1: add_sub_qe8" {  } { { "db/add_sub_qe8.tdf" "" { Text "E:/Electronic Competition/maxmin/db/add_sub_qe8.tdf" 24 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_re8.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/add_sub_re8.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_re8 " "Info: Found entity 1: add_sub_re8" {  } { { "db/add_sub_re8.tdf" "" { Text "E:/Electronic Competition/maxmin/db/add_sub_re8.tdf" 24 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_qa8.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/add_sub_qa8.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_qa8 " "Info: Found entity 1: add_sub_qa8" {  } { { "db/add_sub_qa8.tdf" "" { Text "E:/Electronic Competition/maxmin/db/add_sub_qa8.tdf" 24 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/lpm_divide_klf.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/lpm_divide_klf.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_divide_klf " "Info: Found entity 1: lpm_divide_klf" {  } { { "db/lpm_divide_klf.tdf" "" { Text "E:/Electronic Competition/maxmin/db/lpm_divide_klf.tdf" 24 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/sign_div_unsign_mhg.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/sign_div_unsign_mhg.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 sign_div_unsign_mhg " "Info: Found entity 1: sign_div_unsign_mhg" {  } { { "db/sign_div_unsign_mhg.tdf" "" { Text "E:/Electronic Competition/maxmin/db/sign_div_unsign_mhg.tdf" 26 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/alt_u_div_hld.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/alt_u_div_hld.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 alt_u_div_hld " "Info: Found entity 1: alt_u_div_hld" {  } { { "db/alt_u_div_hld.tdf" "" { Text "E:/Electronic Competition/maxmin/db/alt_u_div_hld.tdf" 32 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/add_sub_ma8.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/add_sub_ma8.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 add_sub_ma8 " "Info: Found entity 1: add_sub_ma8" {  } { { "db/add_sub_ma8.tdf" "" { Text "E:/Electronic Competition/maxmin/db/add_sub_ma8.tdf" 24 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "796 " "Info: Implemented 796 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "10 " "Info: Implemented 10 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "27 " "Info: Implemented 27 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "759 " "Info: Implemented 759 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 66 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 66 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Wed May 21 14:30:25 2008 " "Info: Processing ended: Wed May 21 14:30:25 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:09 " "Info: Elapsed time: 00:00:09" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}

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