maxmin.fit.qmsg

一个自己编写的这次2008北京市电子竞赛VHDL源程序

{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "ADC0820:inst\|lock Global clock " "Info: Automatically promoted some destinations of signal \"ADC0820:inst\|lock\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "lovk " "Info: Destination \"lovk\" may be non-global or may not use global clock" {  } { { "maxmin.bdf" "" { Schematic "E:/Electronic Competition/maxmin/maxmin.bdf" { { 496 424 600 512 "lovk" "" } } } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "ADC0820:inst\|lock " "Info: Destination \"ADC0820:inst\|lock\" may be non-global or may not use global clock" {  } { { "ADC0820.vhd" "" { Text "E:/Electronic Competition/maxmin/ADC0820.vhd" 24 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0}  } { { "ADC0820.vhd" "" { Text "E:/Electronic Competition/maxmin/ADC0820.vhd" 24 -1 0 } }  } 0 0 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "ADC0820:inst\|clko Global clock " "Info: Automatically promoted signal \"ADC0820:inst\|clko\" to use Global clock" {  } { { "ADC0820.vhd" "" { Text "E:/Electronic Competition/maxmin/ADC0820.vhd" 20 -1 0 } }  } 0 0 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "en Global clock " "Info: Automatically promoted some destinations of signal \"en\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "calculate:inst2\|min\[7\]~210 " "Info: Destination \"calculate:inst2\|min\[7\]~210\" may be non-global or may not use global clock" {  } { { "calculate.vhd" "" { Text "E:/Electronic Competition/maxmin/calculate.vhd" 54 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "calculate:inst2\|min\[7\]~211 " "Info: Destination \"calculate:inst2\|min\[7\]~211\" may be non-global or may not use global clock" {  } { { "calculate.vhd" "" { Text "E:/Electronic Competition/maxmin/calculate.vhd" 54 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "calculate:inst2\|min\[4\]~212 " "Info: Destination \"calculate:inst2\|min\[4\]~212\" may be non-global or may not use global clock" {  } { { "calculate.vhd" "" { Text "E:/Electronic Competition/maxmin/calculate.vhd" 54 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "calculate:inst2\|min\[4\]~213 " "Info: Destination \"calculate:inst2\|min\[4\]~213\" may be non-global or may not use global clock" {  } { { "calculate.vhd" "" { Text "E:/Electronic Competition/maxmin/calculate.vhd" 54 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "calculate:inst2\|min\[3\]~214 " "Info: Destination \"calculate:inst2\|min\[3\]~214\" may be non-global or may not use global clock" {  } { { "calculate.vhd" "" { Text "E:/Electronic Competition/maxmin/calculate.vhd" 54 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "calculate:inst2\|min\[3\]~215 " "Info: Destination \"calculate:inst2\|min\[3\]~215\" may be non-global or may not use global clock" {  } { { "calculate.vhd" "" { Text "E:/Electronic Competition/maxmin/calculate.vhd" 54 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "calculate:inst2\|min\[6\]~216 " "Info: Destination \"calculate:inst2\|min\[6\]~216\" may be non-global or may not use global clock" {  } { { "calculate.vhd" "" { Text "E:/Electronic Competition/maxmin/calculate.vhd" 54 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "calculate:inst2\|min\[6\]~217 " "Info: Destination \"calculate:inst2\|min\[6\]~217\" may be non-global or may not use global clock" {  } { { "calculate.vhd" "" { Text "E:/Electronic Competition/maxmin/calculate.vhd" 54 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "calculate:inst2\|min\[5\]~218 " "Info: Destination \"calculate:inst2\|min\[5\]~218\" may be non-global or may not use global clock" {  } { { "calculate.vhd" "" { Text "E:/Electronic Competition/maxmin/calculate.vhd" 54 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "calculate:inst2\|min\[5\]~219 " "Info: Destination \"calculate:inst2\|min\[5\]~219\" may be non-global or may not use global clock" {  } { { "calculate.vhd" "" { Text "E:/Electronic Competition/maxmin/calculate.vhd" 54 -1 0 } }  } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_LIMITED_TO_SUB" "10 " "Info: Limited to 10 non-global destinations" {  } {  } 0 0 "Limited to %1!d! non-global destinations" 0 0}  } { { "maxmin.bdf" "" { Schematic "E:/Electronic Competition/maxmin/maxmin.bdf" { { 344 200 368 360 "en" "" } } } }  } 0 0 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0}
{ "Info" "IFYGR_FYGR_PIN_USES_INTERNAL_GLOBAL" "en " "Info: Pin \"en\" drives global clock, but is not placed in a dedicated clock pin position" {  } { { "maxmin.bdf" "" { Schematic "E:/Electronic Competition/maxmin/maxmin.bdf" { { 344 200 368 360 "en" "" } } } } { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "en" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "maxmin" "UNKNOWN" "V1" "E:/Electronic Competition/maxmin/db/maxmin.quartus_db" { Floorplan "E:/Electronic Competition/maxmin/" "" "" { en } "NODE_NAME" } "" } } { "E:/Electronic Competition/maxmin/maxmin.fld" "" { Floorplan "E:/Electronic Competition/maxmin/maxmin.fld" "" "" { en } "NODE_NAME" } }  } 0 0 "Pin \"%1!s!\" drives global clock, but is not placed in a dedicated clock pin position" 0 0}
{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_ALL_TO_GLOBAL" "calculate:inst2\|LessThan~210 Global clock " "Info: Automatically promoted signal \"calculate:inst2\|LessThan~210\" to use Global clock" {  } { { "c:/altera/quartus51/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus51/bin/Assignment Editor.qase" 1 { { 0 "calculate:inst2\|LessThan~210" } } } } { "c:/altera/quartus51/bin/Report_Window_01.qrpt" "" { Report "c:/altera/quartus51/bin/Report_Window_01.qrpt" "Compiler" "maxmin" "UNKNOWN" "V1" "E:/Electronic Competition/maxmin/db/maxmin.quartus_db" { Floorplan "E:/Electronic Competition/maxmin/" "" "" { calculate:inst2|LessThan~210 } "NODE_NAME" } "" } } { "E:/Electronic Competition/maxmin/maxmin.fld" "" { Floorplan "E:/Electronic Competition/maxmin/maxmin.fld" "" "" { calculate:inst2|LessThan~210 } "NODE_NAME" } }  } 0 0 "Automatically promoted signal \"%1!s!\" to use %2!s!" 0 0}
{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Info: Completed Auto Global Promotion Operation" {  } {  } 0 0 "Completed %1!s!" 0 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Info: Starting register packing" {  } {  } 0 0 "Starting register packing" 0 0}