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📄 lpm_divide_klf.tdf

📁 一个自己编写的这次2008北京市电子竞赛VHDL源程序
💻 TDF
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--lpm_divide DEVICE_FAMILY="Cyclone" LPM_DREPRESENTATION="UNSIGNED" LPM_NREPRESENTATION="UNSIGNED" LPM_WIDTHD=4 LPM_WIDTHN=8 OPTIMIZE_FOR_SPEED=5 denom numer quotient
--VERSION_BEGIN 5.1 cbx_cycloneii 2005:08:30:10:31:44:SJ cbx_lpm_abs 2005:08:17:17:24:32:SJ cbx_lpm_add_sub 2005:09:30:12:13:06:SJ cbx_lpm_divide 2005:03:24:20:40:32:SJ cbx_mgl 2005:10:09:07:39:04:SJ cbx_stratix 2005:10:07:15:53:08:SJ cbx_stratixii 2005:07:27:05:50:56:SJ cbx_util_mgl 2005:09:13:05:23:22:SJ  VERSION_END


--  Copyright (C) 1991-2005 Altera Corporation
--  Your use of Altera Corporation's design tools, logic functions 
--  and other software and tools, and its AMPP partner logic 
--  functions, and any output files any of the foregoing 
--  (including device programming or simulation files), and any 
--  associated documentation or information are expressly subject 
--  to the terms and conditions of the Altera Program License 
--  Subscription Agreement, Altera MegaCore Function License 
--  Agreement, or other applicable license agreement, including, 
--  without limitation, that your use is for the sole purpose of 
--  programming logic devices manufactured by Altera and sold by 
--  Altera or its authorized distributors.  Please refer to the 
--  applicable agreement for further details.


FUNCTION sign_div_unsign_mhg (denominator[3..0], numerator[7..0])
RETURNS ( quotient[7..0], remainder[3..0]);

--synthesis_resources = lut 5 
SUBDESIGN lpm_divide_klf
( 
	denom[3..0]	:	input;
	numer[7..0]	:	input;
	quotient[7..0]	:	output;
	remain[3..0]	:	output;
) 
VARIABLE 
	divider : sign_div_unsign_mhg;
	numer_tmp[7..0]	: WIRE;

BEGIN 
	divider.denominator[] = denom[];
	divider.numerator[] = numer_tmp[];
	numer_tmp[] = numer[];
	quotient[] = divider.quotient[];
	remain[] = divider.remainder[];
END;
--VALID FILE

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