adc0820.vhd

一个自己编写的这次2008北京市电子竞赛VHDL源程序

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity ADC0820 is
	port(
		clk: in std_logic;
		D: in std_logic_vector(7 downto 0);
		RD: out std_logic;
		LOCK0: out std_logic;
		Q: out std_logic_vector(7 downto 0)
	);
end entity ADC0820;

architecture one of ADC0820 is
TYPE ADstates is(st0,st1,st2,st3,st4,st5);
signal current_state, next_state: ADstates :=st0;
signal i: std_logic_vector(4 downto 0);
signal clko: std_logic;
signal lock:std_logic;
begin
lock0<=lock;
	com:process(current_state)
	begin
		case current_state is
		when st0=>  RD<='1';
					next_state<=st1;
					LOCK<='1';
		when st1=>  RD<='0';
					next_state<=st2;
					LOCK<='1';
		when st2=>  RD<='0';
					next_state<=st3;
		when st3=>  RD<='0';
					next_state<=st4;
					LOCK<='1';
		when st4=>  RD<='0';
					next_state<=st5;
					LOCK<='1';
		when st5=>  RD<='0';
					next_state<=st0;
					LOCK<='0';
		when others=>next_state<=st0;
		end case;
	end process com;
	
	clock:process(clk,clko)
	begin
		if(clk 'event and clk='1') then
			i<=i+1;
			clko<=i(4);
			if(clko 'event and clko='1') then current_state<=next_state;
			end if;
		end if;
	end process clock;
	
	LATCH1:PROCESS(lock) --此进程中，在LOCK的上升沿，将转换好的数据锁入
    BEGIN
		IF(lock 'EVENT AND lock='0') THEN Q<=D ; END IF;
    END PROCESS LATCH1 ; 
end one;