display1.vhd

一个自己编写的这次2008北京市电子竞赛VHDL源程序

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use work.mypack.all;      
use ieee.std_logic_unsigned.all;

entity display1 is
	port(
		clkin:in std_logic;
		Dmax: in std_logic_vector(7 downto 0);
		Dmin: in std_logic_vector(7 downto 0);
		Dpp:  in std_logic_vector(7 downto 0);
		en:in bit;
		segoutmax:out std_logic_vector(7 downto 0);
		segoutmin:out std_logic_vector(7 downto 0);
		segoutpp:out std_logic_vector(7 downto 0)
		);
		
end;


architecture one of display1 is

signal segmax :std_logic_vector(7 downto 0);
signal segmin :std_logic_vector(7 downto 0);
signal segpp  :std_logic_vector(7 downto 0);
signal maxmindata:std_logic_vector(7 downto 0);
signal LOCK:std_logic;
		

begin

	process(en,Dmax,Dmin,Dpp)
	begin
	if  en='0' then
		segmax<="00000000";
		segmin<="00000000";
		segpp<="00000000";
		elsif(clkin 'event and clkin='1') then
			segmax<=change(Dmax);
			segmin<=change(Dmin);
			segpp<=change(Dpp);
	end if;
	end process;
	segoutmax<=segmax;
	segoutmin<=segmin;
	segoutpp<=segpp;
end;