maxmin.fit.eqn

一个自己编写的这次2008北京市电子竞赛VHDL源程序

--U14L11 is display1:inst3|lpm_divide:div_rtl_7|lpm_divide_5nf:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_se8:add_sub_11|add_sub_cella[1]~101COUT1_141 at LC_X16_Y6_N5
--operation mode is arithmetic

U14L11_cout_1 = !K3L56 & !K3L55 # !U14L16;
U14L11 = CARRY(U14L11_cout_1);


--K3L77 is display1:inst3|lpm_divide:div_rtl_7|lpm_divide_5nf:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|StageOut[115]~2629 at LC_X20_Y6_N9
--operation mode is normal

K3L77 = !U15L5 & (K3L73 # U14L9 & U14L5);


--U15L9 is display1:inst3|lpm_divide:div_rtl_7|lpm_divide_5nf:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_se8:add_sub_12|add_sub_cella[1]~98 at LC_X16_Y3_N6
--operation mode is arithmetic

U15L9_carry_eqn = (!U15L16 & U15L13) # (U15L16 & U15L14);
U15L9 = U15L9_carry_eqn $ (!K3L72 & !K3L73);

--U15L10 is display1:inst3|lpm_divide:div_rtl_7|lpm_divide_5nf:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_se8:add_sub_12|add_sub_cella[1]~100 at LC_X16_Y3_N6
--operation mode is arithmetic

U15L10_cout_0 = !U15L13 & (K3L72 # K3L73);
U15L10 = CARRY(U15L10_cout_0);

--U15L11 is display1:inst3|lpm_divide:div_rtl_7|lpm_divide_5nf:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_se8:add_sub_12|add_sub_cella[1]~100COUT1_141 at LC_X16_Y3_N6
--operation mode is arithmetic

U15L11_cout_1 = !U15L14 & (K3L72 # K3L73);
U15L11 = CARRY(U15L11_cout_1);


--K3L76 is display1:inst3|lpm_divide:div_rtl_7|lpm_divide_5nf:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|StageOut[115]~28 at LC_X20_Y6_N2
--operation mode is normal

K3L76 = U15L9 & U15L5;


--B1_i[4] is ADC0820:inst|i[4] at LC_X7_Y5_N4
--operation mode is normal

B1_i[4]_lut_out = B1_i[4] $ !B1L25;
B1_i[4] = DFFEAS(B1_i[4]_lut_out, GLOBAL(clk), VCC, , , , , , );


--B1_current_state.st4 is ADC0820:inst|current_state.st4 at LC_X26_Y6_N8
--operation mode is normal

B1_current_state.st4_lut_out = B1_current_state_10;
B1_current_state.st4 = DFFEAS(B1_current_state.st4_lut_out, GLOBAL(clk), VCC, , , , , , );


--B1_current_state.st1 is ADC0820:inst|current_state.st1 at LC_X26_Y6_N3
--operation mode is normal

B1_current_state.st1_lut_out = B1_current_state_4;
B1_current_state.st1 = DFFEAS(B1_current_state.st1_lut_out, GLOBAL(clk), VCC, , , , , , );


--C1_i[15] is calculate:inst2|i[15] at LC_X9_Y6_N6
--operation mode is arithmetic

C1_i[15]_carry_eqn = (!C1L73 & C1L75) # (C1L73 & C1L76);
C1_i[15]_lut_out = C1_i[15] $ (C1_i[15]_carry_eqn);
C1_i[15] = DFFEAS(C1_i[15]_lut_out, !GLOBAL(B1_current_state.st0), VCC, , , , , , );

--C1L78 is calculate:inst2|i[15]~135 at LC_X9_Y6_N6
--operation mode is arithmetic

C1L78_cout_0 = !C1L75 # !C1_i[15];
C1L78 = CARRY(C1L78_cout_0);

--C1L79 is calculate:inst2|i[15]~135COUT1_211 at LC_X9_Y6_N6
--operation mode is arithmetic

C1L79_cout_1 = !C1L76 # !C1_i[15];
C1L79 = CARRY(C1L79_cout_1);


--T1L9 is display1:inst3|lpm_divide:div_rtl_1|lpm_divide_5nf:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_re8:add_sub_7|add_sub_cella[1]~88 at LC_X21_Y9_N6
--operation mode is arithmetic

T1L9_carry_eqn = (!T1L13 & T1L26) # (T1L13 & T1L27);
T1L9 = EB2L17 $ (!T1L9_carry_eqn);

--T1L10 is display1:inst3|lpm_divide:div_rtl_1|lpm_divide_5nf:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_re8:add_sub_7|add_sub_cella[1]~90 at LC_X21_Y9_N6
--operation mode is arithmetic

T1L10_cout_0 = EB2L17 & (!T1L26);
T1L10 = CARRY(T1L10_cout_0);

--T1L11 is display1:inst3|lpm_divide:div_rtl_1|lpm_divide_5nf:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_re8:add_sub_7|add_sub_cella[1]~90COUT1_126 at LC_X21_Y9_N6
--operation mode is arithmetic

T1L11_cout_1 = EB2L17 & (!T1L27);
T1L11 = CARRY(T1L11_cout_1);


--Q2L6 is display1:inst3|lpm_divide:div_rtl_2|lpm_divide_klf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|add_sub_oe8:add_sub_4|add_sub_cella[2]~54 at LC_X22_Y7_N2
--operation mode is arithmetic

Q2L6 = U5L5 $ !Q2L10;

--Q2L7 is display1:inst3|lpm_divide:div_rtl_2|lpm_divide_klf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|add_sub_oe8:add_sub_4|add_sub_cella[2]~56 at LC_X22_Y7_N2
--operation mode is arithmetic

Q2L7_cout_0 = !U5L5 & !Q2L10;
Q2L7 = CARRY(Q2L7_cout_0);

--Q2L8 is display1:inst3|lpm_divide:div_rtl_2|lpm_divide_klf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|add_sub_oe8:add_sub_4|add_sub_cella[2]~56COUT1_73 at LC_X22_Y7_N2
--operation mode is arithmetic

Q2L8_cout_1 = !U5L5 & !Q2L11;
Q2L8 = CARRY(Q2L8_cout_1);


--Y1L5 is display1:inst3|lpm_divide:div_rtl_2|lpm_divide_klf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|StageOut[23]~31 at LC_X22_Y8_N8
--operation mode is normal

Y1L5 = !Q2L14 & (T1L5);


--Y1L6 is display1:inst3|lpm_divide:div_rtl_2|lpm_divide_klf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|StageOut[23]~36 at LC_X22_Y7_N4
--operation mode is normal

Y1L6 = Q2L14 & (T1L5 $ Q2L5);


--Q3L9 is display1:inst3|lpm_divide:div_rtl_2|lpm_divide_klf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|add_sub_oe8:add_sub_5|add_sub_cella[2]~56 at LC_X23_Y7_N2
--operation mode is arithmetic

Q3L9 = Q3L13 $ (!Y1L4 & !Y1L3);

--Q3L10 is display1:inst3|lpm_divide:div_rtl_2|lpm_divide_klf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|add_sub_oe8:add_sub_5|add_sub_cella[2]~58 at LC_X23_Y7_N2
--operation mode is arithmetic

Q3L10_cout_0 = !Q3L13 & (Y1L4 # Y1L3);
Q3L10 = CARRY(Q3L10_cout_0);

--Q3L11 is display1:inst3|lpm_divide:div_rtl_2|lpm_divide_klf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|add_sub_oe8:add_sub_5|add_sub_cella[2]~58COUT1_76 at LC_X23_Y7_N2
--operation mode is arithmetic

Q3L11_cout_1 = !Q3L14 & (Y1L4 # Y1L3);
Q3L11 = CARRY(Q3L11_cout_1);


--Y1L12 is display1:inst3|lpm_divide:div_rtl_2|lpm_divide_klf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|StageOut[28]~413 at LC_X22_Y8_N9
--operation mode is normal

Y1L12 = !Q3L5 & (Q2L14 & (Q2L6) # !Q2L14 & U5L5);


--Y1L11 is display1:inst3|lpm_divide:div_rtl_2|lpm_divide_klf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|StageOut[28]~26 at LC_X23_Y7_N8
--operation mode is normal

Y1L11 = Q3L9 & (Q3L5);


--Q4L9 is display1:inst3|lpm_divide:div_rtl_2|lpm_divide_klf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|add_sub_oe8:add_sub_6|add_sub_cella[2]~56 at LC_X25_Y7_N2
--operation mode is arithmetic

Q4L9 = Q4L13 $ (!Y1L9 & !Y1L10);

--Q4L10 is display1:inst3|lpm_divide:div_rtl_2|lpm_divide_klf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|add_sub_oe8:add_sub_6|add_sub_cella[2]~58 at LC_X25_Y7_N2
--operation mode is arithmetic

Q4L10_cout_0 = !Q4L13 & (Y1L9 # Y1L10);
Q4L10 = CARRY(Q4L10_cout_0);

--Q4L11 is display1:inst3|lpm_divide:div_rtl_2|lpm_divide_klf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|add_sub_oe8:add_sub_6|add_sub_cella[2]~58COUT1_76 at LC_X25_Y7_N2
--operation mode is arithmetic

Q4L11_cout_1 = !Q4L14 & (Y1L9 # Y1L10);
Q4L11 = CARRY(Q4L11_cout_1);


--Q2_add_sub_cella[1] is display1:inst3|lpm_divide:div_rtl_2|lpm_divide_klf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|add_sub_oe8:add_sub_4|add_sub_cella[1] at LC_X22_Y7_N5
--operation mode is arithmetic

Q2_add_sub_cella[1] = U6L8;

--Q2L3 is display1:inst3|lpm_divide:div_rtl_2|lpm_divide_klf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|add_sub_oe8:add_sub_4|add_sub_cella[1]~COUT at LC_X22_Y7_N5
--operation mode is arithmetic

Q2L3_cout_0 = U6L8;
Q2L3 = CARRY(Q2L3_cout_0);

--Q2L4 is display1:inst3|lpm_divide:div_rtl_2|lpm_divide_klf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|add_sub_oe8:add_sub_4|add_sub_cella[1]~COUTCOUT1 at LC_X22_Y7_N5
--operation mode is arithmetic

Q2L4_cout_1 = U6L8;
Q2L4 = CARRY(Q2L4_cout_1);


--Y1L10 is display1:inst3|lpm_divide:div_rtl_2|lpm_divide_klf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|StageOut[27]~414 at LC_X22_Y8_N5
--operation mode is normal

Y1L10 = !Q3L5 & (Q2L14 & (!Q2_add_sub_cella[1]) # !Q2L14 & U6L8);


--Q3L12 is display1:inst3|lpm_divide:div_rtl_2|lpm_divide_klf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|add_sub_oe8:add_sub_5|add_sub_cella[2]~61 at LC_X23_Y7_N1
--operation mode is arithmetic

Q3L12 = Q3L16 $ (!Y1L2 & !Y1L1);

--Q3L13 is display1:inst3|lpm_divide:div_rtl_2|lpm_divide_klf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|add_sub_oe8:add_sub_5|add_sub_cella[2]~63 at LC_X23_Y7_N1
--operation mode is arithmetic

Q3L13_cout_0 = !Y1L2 & !Y1L1 & !Q3L16;
Q3L13 = CARRY(Q3L13_cout_0);

--Q3L14 is display1:inst3|lpm_divide:div_rtl_2|lpm_divide_klf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|add_sub_oe8:add_sub_5|add_sub_cella[2]~63COUT1 at LC_X23_Y7_N1
--operation mode is arithmetic

Q3L14_cout_1 = !Y1L2 & !Y1L1 & !Q3L17;
Q3L14 = CARRY(Q3L14_cout_1);


--Y1L20 is display1:inst3|lpm_divide:div_rtl_2|lpm_divide_klf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|StageOut[33]~415 at LC_X22_Y8_N2
--operation mode is normal

Y1L20 = !Q4L5 & (Y1L10 # Q3L12 & Q3L5);


--Y1L19 is display1:inst3|lpm_divide:div_rtl_2|lpm_divide_klf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|StageOut[33]~16 at LC_X25_Y7_N5
--operation mode is normal

Y1L19 = Q4L9 & (Q4L5);


--Q5L6 is display1:inst3|lpm_divide:div_rtl_2|lpm_divide_klf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|add_sub_oe8:add_sub_7|add_sub_cella[2]~58 at LC_X25_Y8_N7
--operation mode is arithmetic

Q5L6_cout_0 = !Q5L9 & (Y1L18 # Y1L17);
Q5L6 = CARRY(Q5L6_cout_0);

--Q5L7 is display1:inst3|lpm_divide:div_rtl_2|lpm_divide_klf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|add_sub_oe8:add_sub_7|add_sub_cella[2]~58COUT1_73 at LC_X25_Y8_N7
--operation mode is arithmetic

Q5L7_cout_1 = !Q5L10 & (Y1L18 # Y1L17);
Q5L7 = CARRY(Q5L7_cout_1);


--T1L12 is display1:inst3|lpm_divide:div_rtl_1|lpm_divide_5nf:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_re8:add_sub_7|add_sub_cella[1]~93 at LC_X21_Y9_N4
--operation mode is arithmetic

T1L12 = EB2L4 $ (!T1L17);

--T1L13 is display1:inst3|lpm_divide:div_rtl_1|lpm_divide_5nf:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_re8:add_sub_7|add_sub_cella[1]~95 at LC_X21_Y9_N4
--operation mode is arithmetic

T1L13 = T1L14;


--EB2L4 is display1:inst3|lpm_mult:mult_rtl_0|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~87 at LC_X20_Y9_N6
--operation mode is arithmetic

EB2L4_carry_eqn = (!EB2L11 & EB2L8) # (EB2L11 & EB2L9);
EB2L4 = AB1L10 $ (!EB2L4_carry_eqn);

--EB2L5 is display1:inst3|lpm_mult:mult_rtl_0|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~89 at LC_X20_Y9_N6
--operation mode is arithmetic

EB2L5_cout_0 = AB1L10 & (!EB2L8);
EB2L5 = CARRY(EB2L5_cout_0);

--EB2L6 is display1:inst3|lpm_mult:mult_rtl_0|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~89COUT1_132 at LC_X20_Y9_N6
--operation mode is arithmetic

EB2L6_cout_1 = AB1L10 & (!EB2L9);
EB2L6 = CARRY(EB2L6_cout_1);


--K1L28 is display1:inst3|lpm_divide:div_rtl_1|lpm_divide_5nf:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|StageOut[78]~2629 at LC_X21_Y11_N5
--operation mode is normal

K1L28 = !U5L5 & (T1L5 & T1L12 # !T1L5 & (EB2L4));


--U5L9 is display1:inst3|lpm_divide:div_rtl_1|lpm_divide_5nf:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_se8:add_sub_8|add_sub_cella[1]~98 at LC_X20_Y11_N5
--operation mode is arithmetic

U5L9_carry_eqn = (!U5L13 & GND) # (U5L13 & VCC);
U5L9 = U5L9_carry_eqn $ (K1L10 # K1L11);

--U5L10 is display1:inst3|lpm_divide:div_rtl_1|lpm_divide_5nf:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_se8:add_sub_8|add_sub_cella[1]~100 at LC_X20_Y11_N5
--operation mode is arithmetic

U5L10_cout_0 = !K1L10 & !K1L11 # !U5L13;
U5L10 = CARRY(U5L10_cout_0);

--U5L11 is display1:inst3|lpm_divide:div_rtl_1|lpm_divide_5nf:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_se8:add_sub_8|add_sub_cella[1]~100COUT1_140 at LC_X20_Y11_N5
--operation mode is arithmetic

U5L11_cout_1 = !K1L10 & !K1L11 # !U5L13;
U5L11 = CARRY(U5L11_cout_1);


--K1L45 is display1:inst3|lpm_divide:div_rtl_1|lpm_divide_5nf:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|StageOut[88]~2630 at LC_X23_Y11_N9
--operation mode is normal

K1L45 = !U6L8 & (K1L28 # U5L5 & U5L9);


--U6L9 is display1:inst3|lpm_divide:div_rtl_1|lpm_divide_5nf:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_se8:add_sub_9|add_sub_cella[1]~99 at LC_X22_Y10_N6
--operation mode is arithmetic

U6L9_carry_eqn = (!U6L16 & U6L13) # (U6L16 & U6L14);
U6L9 = U6L9_carry_eqn $ (!K1L28 & !K1L27);

--U6L10 is display1:inst3|lpm_divide:div_rtl_1|lpm_divide_5nf:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_se8:add_sub_9|add_sub_cella[1]~101 at LC_X22_Y10_N6
--operation mode is arithmetic

U6L10_cout_0 = !U6L13 & (K1L28 # K1L27);
U6L10