maxmin.fit.eqn

一个自己编写的这次2008北京市电子竞赛VHDL源程序

--U12L6 is display1:inst3|lpm_divide:div_rtl_4|lpm_divide_5nf:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_se8:add_sub_9|add_sub_cella[1]~94 at LC_X11_Y10_N3
--operation mode is arithmetic

U12L6 = U12L23 $ (K2L21 # K2L22);

--U12L7 is display1:inst3|lpm_divide:div_rtl_4|lpm_divide_5nf:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_se8:add_sub_9|add_sub_cella[1]~96 at LC_X11_Y10_N3
--operation mode is arithmetic

U12L7_cout_0 = !K2L21 & !K2L22 # !U12L23;
U12L7 = CARRY(U12L7_cout_0);

--U12L8 is display1:inst3|lpm_divide:div_rtl_4|lpm_divide_5nf:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_se8:add_sub_9|add_sub_cella[1]~96COUT1 at LC_X11_Y10_N3
--operation mode is arithmetic

U12L8_cout_1 = !K2L21 & !K2L22 # !U12L24;
U12L8 = CARRY(U12L8_cout_1);


--K2L56 is display1:inst3|lpm_divide:div_rtl_4|lpm_divide_5nf:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|StageOut[95]~2627 at LC_X12_Y8_N6
--operation mode is normal

K2L56 = !U7L3 & (K2L39 # U12L5 & U12L6);


--U7L7 is display1:inst3|lpm_divide:div_rtl_4|lpm_divide_5nf:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_se8:add_sub_10|add_sub_cella[1]~99 at LC_X15_Y9_N4
--operation mode is arithmetic

U7L7 = U7L18 $ (!K2L39 & !K2L38);

--U7L8 is display1:inst3|lpm_divide:div_rtl_4|lpm_divide_5nf:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_se8:add_sub_10|add_sub_cella[1]~101 at LC_X15_Y9_N4
--operation mode is arithmetic

U7L8 = U7L9;


--K2L73 is display1:inst3|lpm_divide:div_rtl_4|lpm_divide_5nf:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|StageOut[105]~2628 at LC_X12_Y8_N1
--operation mode is normal

K2L73 = !U8L3 & (K2L56 # U7L7 & U7L3);


--U8L7 is display1:inst3|lpm_divide:div_rtl_4|lpm_divide_5nf:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_se8:add_sub_11|add_sub_cella[1]~99 at LC_X15_Y8_N5
--operation mode is arithmetic

U8L7_carry_eqn = (!U8L14 & GND) # (U8L14 & VCC);
U8L7 = U8L7_carry_eqn $ (K2L55 # K2L56);

--U8L8 is display1:inst3|lpm_divide:div_rtl_4|lpm_divide_5nf:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_se8:add_sub_11|add_sub_cella[1]~101 at LC_X15_Y8_N5
--operation mode is arithmetic

U8L8_cout_0 = !K2L55 & !K2L56 # !U8L14;
U8L8 = CARRY(U8L8_cout_0);

--U8L9 is display1:inst3|lpm_divide:div_rtl_4|lpm_divide_5nf:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_se8:add_sub_11|add_sub_cella[1]~101COUT1_140 at LC_X15_Y8_N5
--operation mode is arithmetic

U8L9_cout_1 = !K2L55 & !K2L56 # !U8L14;
U8L9 = CARRY(U8L9_cout_1);


--K2L77 is display1:inst3|lpm_divide:div_rtl_4|lpm_divide_5nf:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|StageOut[115]~2629 at LC_X12_Y8_N2
--operation mode is normal

K2L77 = !U9L3 & (K2L73 # U8L7 & U8L3);


--U9L7 is display1:inst3|lpm_divide:div_rtl_4|lpm_divide_5nf:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_se8:add_sub_12|add_sub_cella[1]~98 at LC_X16_Y9_N6
--operation mode is arithmetic

U9L7_carry_eqn = (!U9L14 & U9L11) # (U9L14 & U9L12);
U9L7 = U9L7_carry_eqn $ (!K2L73 & !K2L72);

--U9L8 is display1:inst3|lpm_divide:div_rtl_4|lpm_divide_5nf:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_se8:add_sub_12|add_sub_cella[1]~100 at LC_X16_Y9_N6
--operation mode is arithmetic

U9L8_cout_0 = !U9L11 & (K2L73 # K2L72);
U9L8 = CARRY(U9L8_cout_0);

--U9L9 is display1:inst3|lpm_divide:div_rtl_4|lpm_divide_5nf:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_se8:add_sub_12|add_sub_cella[1]~100COUT1_140 at LC_X16_Y9_N6
--operation mode is arithmetic

U9L9_cout_1 = !U9L12 & (K2L73 # K2L72);
U9L9 = CARRY(U9L9_cout_1);


--K2L76 is display1:inst3|lpm_divide:div_rtl_4|lpm_divide_5nf:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|StageOut[115]~28 at LC_X12_Y8_N3
--operation mode is normal

K2L76 = U9L3 & U9L7;


--T3L5 is display1:inst3|lpm_divide:div_rtl_7|lpm_divide_5nf:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_re8:add_sub_7|add_sub_cella[1]~78 at LC_X16_Y5_N7
--operation mode is normal

T3L5_carry_eqn = (!T3L13 & T3L10) # (T3L13 & T3L11);
T3L5 = T3L5_carry_eqn;


--Q12L5 is display1:inst3|lpm_divide:div_rtl_8|lpm_divide_klf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|add_sub_oe8:add_sub_4|add_sub_cella[2]~48 at LC_X11_Y4_N9
--operation mode is normal

Q12L5 = !Q12L7;


--Q13L7 is display1:inst3|lpm_divide:div_rtl_8|lpm_divide_klf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|add_sub_oe8:add_sub_5|add_sub_cella[2]~53 at LC_X11_Y6_N3
--operation mode is arithmetic

Q13L7_cout_0 = !Y3L6 & !Y3L5 & !Q13L10;
Q13L7 = CARRY(Q13L7_cout_0);

--Q13L8 is display1:inst3|lpm_divide:div_rtl_8|lpm_divide_klf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|add_sub_oe8:add_sub_5|add_sub_cella[2]~53COUT1_77 at LC_X11_Y6_N3
--operation mode is arithmetic

Q13L8_cout_1 = !Y3L6 & !Y3L5 & !Q13L11;
Q13L8 = CARRY(Q13L8_cout_1);


--Q14L7 is display1:inst3|lpm_divide:div_rtl_8|lpm_divide_klf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|add_sub_oe8:add_sub_6|add_sub_cella[2]~53 at LC_X12_Y6_N3
--operation mode is arithmetic

Q14L7_cout_0 = !Y3L12 & !Y3L11 & !Q14L10;
Q14L7 = CARRY(Q14L7_cout_0);

--Q14L8 is display1:inst3|lpm_divide:div_rtl_8|lpm_divide_klf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|add_sub_oe8:add_sub_6|add_sub_cella[2]~53COUT1_77 at LC_X12_Y6_N3
--operation mode is arithmetic

Q14L8_cout_1 = !Y3L12 & !Y3L11 & !Q14L11;
Q14L8 = CARRY(Q14L8_cout_1);


--Q15L3 is display1:inst3|lpm_divide:div_rtl_8|lpm_divide_klf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|add_sub_oe8:add_sub_7|add_sub_cella[2]~53 at LC_X15_Y3_N8
--operation mode is arithmetic

Q15L3_cout_0 = !Y3L20 & !Y3L19 & !Q15L6;
Q15L3 = CARRY(Q15L3_cout_0);

--Q15L4 is display1:inst3|lpm_divide:div_rtl_8|lpm_divide_klf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|add_sub_oe8:add_sub_7|add_sub_cella[2]~53COUT1_74 at LC_X15_Y3_N8
--operation mode is arithmetic

Q15L4_cout_1 = !Y3L20 & !Y3L19 & !Q15L7;
Q15L4 = CARRY(Q15L4_cout_1);


--U13L7 is display1:inst3|lpm_divide:div_rtl_7|lpm_divide_5nf:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_se8:add_sub_10|add_sub_cella[1]~96 at LC_X19_Y6_N7
--operation mode is arithmetic

U13L7_cout_0 = !K3L44 & !K3L45 & !U13L14;
U13L7 = CARRY(U13L7_cout_0);

--U13L8 is display1:inst3|lpm_divide:div_rtl_7|lpm_divide_5nf:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_se8:add_sub_10|add_sub_cella[1]~96COUT1_143 at LC_X19_Y6_N7
--operation mode is arithmetic

U13L8_cout_1 = !K3L44 & !K3L45 & !U13L15;
U13L8 = CARRY(U13L8_cout_1);


--U14L7 is display1:inst3|lpm_divide:div_rtl_7|lpm_divide_5nf:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_se8:add_sub_11|add_sub_cella[1]~96 at LC_X16_Y6_N7
--operation mode is arithmetic

U14L7_cout_0 = !K3L59 & !K3L60 & !U14L13;
U14L7 = CARRY(U14L7_cout_0);

--U14L8 is display1:inst3|lpm_divide:div_rtl_7|lpm_divide_5nf:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_se8:add_sub_11|add_sub_cella[1]~96COUT1_143 at LC_X16_Y6_N7
--operation mode is arithmetic

U14L8_cout_1 = !K3L59 & !K3L60 & !U14L14;
U14L8 = CARRY(U14L8_cout_1);


--U15L7 is display1:inst3|lpm_divide:div_rtl_7|lpm_divide_5nf:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_se8:add_sub_12|add_sub_cella[1]~95 at LC_X16_Y3_N7
--operation mode is arithmetic

U15L7_cout_0 = !K3L74 & !K3L75 & !U15L10;
U15L7 = CARRY(U15L7_cout_0);

--U15L8 is display1:inst3|lpm_divide:div_rtl_7|lpm_divide_5nf:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_se8:add_sub_12|add_sub_cella[1]~95COUT1_142 at LC_X16_Y3_N7
--operation mode is arithmetic

U15L8_cout_1 = !K3L74 & !K3L75 & !U15L11;
U15L8 = CARRY(U15L8_cout_1);


--T3L6 is display1:inst3|lpm_divide:div_rtl_7|lpm_divide_5nf:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_re8:add_sub_7|add_sub_cella[1]~83 at LC_X16_Y5_N1
--operation mode is arithmetic

T3L6 = EB8L1 $ (T3L23);

--T3L7 is display1:inst3|lpm_divide:div_rtl_7|lpm_divide_5nf:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_re8:add_sub_7|add_sub_cella[1]~85 at LC_X16_Y5_N1
--operation mode is arithmetic

T3L7_cout_0 = !T3L23 # !EB8L1;
T3L7 = CARRY(T3L7_cout_0);

--T3L8 is display1:inst3|lpm_divide:div_rtl_7|lpm_divide_5nf:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_re8:add_sub_7|add_sub_cella[1]~85COUT1_123 at LC_X16_Y5_N1
--operation mode is arithmetic

T3L8_cout_1 = !T3L24 # !EB8L1;
T3L8 = CARRY(T3L8_cout_1);


--EB8L1 is display1:inst3|lpm_mult:mult_rtl_6|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~82 at LC_X17_Y5_N3
--operation mode is arithmetic

EB8L1 = AB3L7 $ AB3L4 $ EB8L15;

--EB8L2 is display1:inst3|lpm_mult:mult_rtl_6|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~84 at LC_X17_Y5_N3
--operation mode is arithmetic

EB8L2_cout_0 = AB3L7 & !AB3L4 & !EB8L15 # !AB3L7 & (!EB8L15 # !AB3L4);
EB8L2 = CARRY(EB8L2_cout_0);

--EB8L3 is display1:inst3|lpm_mult:mult_rtl_6|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~84COUT1 at LC_X17_Y5_N3
--operation mode is arithmetic

EB8L3_cout_1 = AB3L7 & !AB3L4 & !EB8L16 # !AB3L7 & (!EB8L16 # !AB3L4);
EB8L3 = CARRY(EB8L3_cout_1);


--U17L5 is display1:inst3|lpm_divide:div_rtl_7|lpm_divide_5nf:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_se8:add_sub_8|add_sub_cella[1]~88 at LC_X19_Y5_N8
--operation mode is normal

U17L5_carry_eqn = (!U17L13 & U17L20) # (U17L13 & U17L21);
U17L5 = !U17L5_carry_eqn;


--K3L22 is display1:inst3|lpm_divide:div_rtl_7|lpm_divide_5nf:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|StageOut[75]~2625 at LC_X20_Y5_N3
--operation mode is normal

K3L22 = !U17L5 & (T3L5 & (T3L6) # !T3L5 & EB8L1);


--U17L6 is display1:inst3|lpm_divide:div_rtl_7|lpm_divide_5nf:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_se8:add_sub_8|add_sub_cella[1]~93 at LC_X19_Y5_N2
--operation mode is arithmetic

U17L6 = U17L23 $ (!K3L4 & !K3L5);

--U17L7 is display1:inst3|lpm_divide:div_rtl_7|lpm_divide_5nf:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_se8:add_sub_8|add_sub_cella[1]~95 at LC_X19_Y5_N2
--operation mode is arithmetic

U17L7_cout_0 = !U17L23 & (K3L4 # K3L5);
U17L7 = CARRY(U17L7_cout_0);

--U17L8 is display1:inst3|lpm_divide:div_rtl_7|lpm_divide_5nf:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_se8:add_sub_8|add_sub_cella[1]~95COUT1_139 at LC_X19_Y5_N2
--operation mode is arithmetic

U17L8_cout_1 = !U17L24 & (K3L4 # K3L5);
U17L8 = CARRY(U17L8_cout_1);


--U18L5 is display1:inst3|lpm_divide:div_rtl_7|lpm_divide_5nf:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_se8:add_sub_9|add_sub_cella[1]~89 at LC_X19_Y4_N8
--operation mode is normal

U18L5_carry_eqn = (!U18L16 & U18L20) # (U18L16 & U18L21);
U18L5 = !U18L5_carry_eqn;


--K3L39 is display1:inst3|lpm_divide:div_rtl_7|lpm_divide_5nf:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|StageOut[85]~2626 at LC_X20_Y6_N0
--operation mode is normal

K3L39 = !U18L5 & (K3L22 # U17L5 & U17L6);


--U18L6 is display1:inst3|lpm_divide:div_rtl_7|lpm_divide_5nf:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_se8:add_sub_9|add_sub_cella[1]~94 at LC_X19_Y4_N3
--operation mode is arithmetic

U18L6 = U18L23 $ (K3L21 # K3L22);

--U18L7 is display1:inst3|lpm_divide:div_rtl_7|lpm_divide_5nf:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_se8:add_sub_9|add_sub_cella[1]~96 at LC_X19_Y4_N3
--operation mode is arithmetic

U18L7_cout_0 = !K3L21 & !K3L22 # !U18L23;
U18L7 = CARRY(U18L7_cout_0);

--U18L8 is display1:inst3|lpm_divide:div_rtl_7|lpm_divide_5nf:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_se8:add_sub_9|add_sub_cella[1]~96COUT1 at LC_X19_Y4_N3
--operation mode is arithmetic

U18L8_cout_1 = !K3L21 & !K3L22 # !U18L24;
U18L8 = CARRY(U18L8_cout_1);


--K3L56 is display1:inst3|lpm_divide:div_rtl_7|lpm_divide_5nf:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|StageOut[95]~2627 at LC_X20_Y6_N8
--operation mode is normal

K3L56 = !U13L5 & (K3L39 # U18L5 & U18L6);


--U13L9 is display1:inst3|lpm_divide:div_rtl_7|lpm_divide_5nf:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_se8:add_sub_10|add_sub_cella[1]~99 at LC_X19_Y6_N4
--operation mode is arithmetic

U13L9 = U13L20 $ (!K3L38 & !K3L39);

--U13L10 is display1:inst3|lpm_divide:div_rtl_7|lpm_divide_5nf:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_se8:add_sub_10|add_sub_cella[1]~101 at LC_X19_Y6_N4
--operation mode is arithmetic

U13L10 = U13L11;


--K3L73 is display1:inst3|lpm_divide:div_rtl_7|lpm_divide_5nf:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|StageOut[105]~2628 at LC_X20_Y6_N6
--operation mode is normal

K3L73 = !U14L5 & (K3L56 # U13L9 & U13L5);


--U14L9 is display1:inst3|lpm_divide:div_rtl_7|lpm_divide_5nf:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_se8:add_sub_11|add_sub_cella[1]~99 at LC_X16_Y6_N5
--operation mode is arithmetic

U14L9_carry_eqn = (!U14L16 & GND) # (U14L16 & VCC);
U14L9 = U14L9_carry_eqn $ (K3L56 # K3L55);

--U14L10 is display1:inst3|lpm_divide:div_rtl_7|lpm_divide_5nf:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_se8:add_sub_11|add_sub_cella[1]~101 at LC_X16_Y6_N5
--operation mode is arithmetic

U14L10_cout_0 = !K3L56 & !K3L55 # !U14L16;
U14L10 = CARRY(U14L10_cout_0);