maxmin.fit.eqn

一个自己编写的这次2008北京市电子竞赛VHDL源程序

U6L7_cout_1 = !K1L22 & !K1L21 # !U6L21;
U6L7 = CARRY(U6L7_cout_1);


--T1L6 is display1:inst3|lpm_divide:div_rtl_1|lpm_divide_5nf:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_re8:add_sub_7|add_sub_cella[1]~83 at LC_X21_Y9_N1
--operation mode is arithmetic

T1L6 = EB2L1 $ (T1L23);

--T1L7 is display1:inst3|lpm_divide:div_rtl_1|lpm_divide_5nf:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_re8:add_sub_7|add_sub_cella[1]~85 at LC_X21_Y9_N1
--operation mode is arithmetic

T1L7_cout_0 = !T1L23 # !EB2L1;
T1L7 = CARRY(T1L7_cout_0);

--T1L8 is display1:inst3|lpm_divide:div_rtl_1|lpm_divide_5nf:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_re8:add_sub_7|add_sub_cella[1]~85COUT1_123 at LC_X21_Y9_N1
--operation mode is arithmetic

T1L8_cout_1 = !T1L24 # !EB2L1;
T1L8 = CARRY(T1L8_cout_1);


--EB2L1 is display1:inst3|lpm_mult:mult_rtl_0|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~82 at LC_X20_Y9_N3
--operation mode is arithmetic

EB2L1 = AB1L7 $ AB1L4 $ EB2L15;

--EB2L2 is display1:inst3|lpm_mult:mult_rtl_0|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~84 at LC_X20_Y9_N3
--operation mode is arithmetic

EB2L2_cout_0 = AB1L7 & !AB1L4 & !EB2L15 # !AB1L7 & (!EB2L15 # !AB1L4);
EB2L2 = CARRY(EB2L2_cout_0);

--EB2L3 is display1:inst3|lpm_mult:mult_rtl_0|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~84COUT1 at LC_X20_Y9_N3
--operation mode is arithmetic

EB2L3_cout_1 = AB1L7 & !AB1L4 & !EB2L16 # !AB1L7 & (!EB2L16 # !AB1L4);
EB2L3 = CARRY(EB2L3_cout_1);


--U5L5 is display1:inst3|lpm_divide:div_rtl_1|lpm_divide_5nf:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_se8:add_sub_8|add_sub_cella[1]~88 at LC_X20_Y11_N8
--operation mode is normal

U5L5_carry_eqn = (!U5L13 & U5L20) # (U5L13 & U5L21);
U5L5 = !U5L5_carry_eqn;


--K1L22 is display1:inst3|lpm_divide:div_rtl_1|lpm_divide_5nf:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|StageOut[75]~2625 at LC_X22_Y9_N3
--operation mode is normal

K1L22 = !U5L5 & (T1L5 & T1L6 # !T1L5 & (EB2L1));


--U5L6 is display1:inst3|lpm_divide:div_rtl_1|lpm_divide_5nf:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_se8:add_sub_8|add_sub_cella[1]~93 at LC_X20_Y11_N2
--operation mode is arithmetic

U5L6 = U5L23 $ (!K1L5 & !K1L4);

--U5L7 is display1:inst3|lpm_divide:div_rtl_1|lpm_divide_5nf:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_se8:add_sub_8|add_sub_cella[1]~95 at LC_X20_Y11_N2
--operation mode is arithmetic

U5L7_cout_0 = !U5L23 & (K1L5 # K1L4);
U5L7 = CARRY(U5L7_cout_0);

--U5L8 is display1:inst3|lpm_divide:div_rtl_1|lpm_divide_5nf:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_se8:add_sub_8|add_sub_cella[1]~95COUT1_139 at LC_X20_Y11_N2
--operation mode is arithmetic

U5L8_cout_1 = !U5L24 & (K1L5 # K1L4);
U5L8 = CARRY(U5L8_cout_1);


--K1L21 is display1:inst3|lpm_divide:div_rtl_1|lpm_divide_5nf:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|StageOut[75]~104 at LC_X23_Y9_N6
--operation mode is normal

K1L21 = U5L6 & (U5L5);


--U6L8 is display1:inst3|lpm_divide:div_rtl_1|lpm_divide_5nf:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_se8:add_sub_9|add_sub_cella[1]~94 at LC_X22_Y10_N8
--operation mode is normal

U6L8_carry_eqn = (!U6L16 & U6L23) # (U6L16 & U6L24);
U6L8 = !U6L8_carry_eqn;


--K1L56 is display1:inst3|lpm_divide:div_rtl_1|lpm_divide_5nf:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|StageOut[95]~2626 at LC_X23_Y9_N0
--operation mode is normal

K1L56 = U6L8 & (U6L5) # !U6L8 & (K1L21 # K1L22);


--K1L74 is display1:inst3|lpm_divide:div_rtl_1|lpm_divide_5nf:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|StageOut[105]~2627 at LC_X23_Y9_N1
--operation mode is normal

K1L74 = !U2L3 & (U1L3 & (U1L7) # !U1L3 & K1L56);


--U2L7 is display1:inst3|lpm_divide:div_rtl_1|lpm_divide_5nf:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_se8:add_sub_11|add_sub_cella[1]~99 at LC_X24_Y9_N5
--operation mode is arithmetic

U2L7_carry_eqn = (!U2L14 & GND) # (U2L14 & VCC);
U2L7 = U2L7_carry_eqn $ (K1L55 # K1L57);

--U2L8 is display1:inst3|lpm_divide:div_rtl_1|lpm_divide_5nf:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_se8:add_sub_11|add_sub_cella[1]~101 at LC_X24_Y9_N5
--operation mode is arithmetic

U2L8_cout_0 = !K1L55 & !K1L57 # !U2L14;
U2L8 = CARRY(U2L8_cout_0);

--U2L9 is display1:inst3|lpm_divide:div_rtl_1|lpm_divide_5nf:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_se8:add_sub_11|add_sub_cella[1]~101COUT1_140 at LC_X24_Y9_N5
--operation mode is arithmetic

U2L9_cout_1 = !K1L55 & !K1L57 # !U2L14;
U2L9 = CARRY(U2L9_cout_1);


--K1L78 is display1:inst3|lpm_divide:div_rtl_1|lpm_divide_5nf:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|StageOut[115]~2628 at LC_X23_Y9_N2
--operation mode is normal

K1L78 = !U3L3 & (K1L74 # U2L3 & U2L7);


--U3L7 is display1:inst3|lpm_divide:div_rtl_1|lpm_divide_5nf:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_se8:add_sub_12|add_sub_cella[1]~98 at LC_X24_Y8_N6
--operation mode is arithmetic

U3L7_carry_eqn = (!U3L14 & U3L11) # (U3L14 & U3L12);
U3L7 = U3L7_carry_eqn $ (!K1L74 & !K1L73);

--U3L8 is display1:inst3|lpm_divide:div_rtl_1|lpm_divide_5nf:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_se8:add_sub_12|add_sub_cella[1]~100 at LC_X24_Y8_N6
--operation mode is arithmetic

U3L8_cout_0 = !U3L11 & (K1L74 # K1L73);
U3L8 = CARRY(U3L8_cout_0);

--U3L9 is display1:inst3|lpm_divide:div_rtl_1|lpm_divide_5nf:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_se8:add_sub_12|add_sub_cella[1]~100COUT1_140 at LC_X24_Y8_N6
--operation mode is arithmetic

U3L9_cout_1 = !U3L12 & (K1L74 # K1L73);
U3L9 = CARRY(U3L9_cout_1);


--K1L77 is display1:inst3|lpm_divide:div_rtl_1|lpm_divide_5nf:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|StageOut[115]~28 at LC_X23_Y9_N5
--operation mode is normal

K1L77 = U3L3 & U3L7;


--T2L5 is display1:inst3|lpm_divide:div_rtl_4|lpm_divide_5nf:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_re8:add_sub_7|add_sub_cella[1]~78 at LC_X12_Y10_N7
--operation mode is normal

T2L5_carry_eqn = (!T2L13 & T2L10) # (T2L13 & T2L11);
T2L5 = T2L5_carry_eqn;


--Q7L5 is display1:inst3|lpm_divide:div_rtl_5|lpm_divide_klf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|add_sub_oe8:add_sub_4|add_sub_cella[2]~48 at LC_X9_Y8_N3
--operation mode is normal

Q7L5 = !Q7L7;


--Q8L7 is display1:inst3|lpm_divide:div_rtl_5|lpm_divide_klf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|add_sub_oe8:add_sub_5|add_sub_cella[2]~53 at LC_X10_Y8_N3
--operation mode is arithmetic

Q8L7_cout_0 = !Y2L6 & !Y2L5 & !Q8L10;
Q8L7 = CARRY(Q8L7_cout_0);

--Q8L8 is display1:inst3|lpm_divide:div_rtl_5|lpm_divide_klf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|add_sub_oe8:add_sub_5|add_sub_cella[2]~53COUT1_77 at LC_X10_Y8_N3
--operation mode is arithmetic

Q8L8_cout_1 = !Y2L6 & !Y2L5 & !Q8L11;
Q8L8 = CARRY(Q8L8_cout_1);


--Q9L7 is display1:inst3|lpm_divide:div_rtl_5|lpm_divide_klf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|add_sub_oe8:add_sub_6|add_sub_cella[2]~53 at LC_X10_Y7_N3
--operation mode is arithmetic

Q9L7_cout_0 = !Y2L12 & !Y2L11 & !Q9L10;
Q9L7 = CARRY(Q9L7_cout_0);

--Q9L8 is display1:inst3|lpm_divide:div_rtl_5|lpm_divide_klf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|add_sub_oe8:add_sub_6|add_sub_cella[2]~53COUT1_77 at LC_X10_Y7_N3
--operation mode is arithmetic

Q9L8_cout_1 = !Y2L12 & !Y2L11 & !Q9L11;
Q9L8 = CARRY(Q9L8_cout_1);


--Q10L3 is display1:inst3|lpm_divide:div_rtl_5|lpm_divide_klf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|add_sub_oe8:add_sub_7|add_sub_cella[2]~53 at LC_X11_Y7_N3
--operation mode is arithmetic

Q10L3_cout_0 = !Y2L19 & !Y2L20 & !Q10L6;
Q10L3 = CARRY(Q10L3_cout_0);

--Q10L4 is display1:inst3|lpm_divide:div_rtl_5|lpm_divide_klf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|add_sub_oe8:add_sub_7|add_sub_cella[2]~53COUT1_74 at LC_X11_Y7_N3
--operation mode is arithmetic

Q10L4_cout_1 = !Y2L19 & !Y2L20 & !Q10L7;
Q10L4 = CARRY(Q10L4_cout_1);


--U7L5 is display1:inst3|lpm_divide:div_rtl_4|lpm_divide_5nf:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_se8:add_sub_10|add_sub_cella[1]~96 at LC_X15_Y9_N7
--operation mode is arithmetic

U7L5_cout_0 = !K2L45 & !K2L44 & !U7L12;
U7L5 = CARRY(U7L5_cout_0);

--U7L6 is display1:inst3|lpm_divide:div_rtl_4|lpm_divide_5nf:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_se8:add_sub_10|add_sub_cella[1]~96COUT1_142 at LC_X15_Y9_N7
--operation mode is arithmetic

U7L6_cout_1 = !K2L45 & !K2L44 & !U7L13;
U7L6 = CARRY(U7L6_cout_1);


--U8L5 is display1:inst3|lpm_divide:div_rtl_4|lpm_divide_5nf:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_se8:add_sub_11|add_sub_cella[1]~96 at LC_X15_Y8_N7
--operation mode is arithmetic

U8L5_cout_0 = !K2L59 & !K2L60 & !U8L11;
U8L5 = CARRY(U8L5_cout_0);

--U8L6 is display1:inst3|lpm_divide:div_rtl_4|lpm_divide_5nf:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_se8:add_sub_11|add_sub_cella[1]~96COUT1_142 at LC_X15_Y8_N7
--operation mode is arithmetic

U8L6_cout_1 = !K2L59 & !K2L60 & !U8L12;
U8L6 = CARRY(U8L6_cout_1);


--U9L5 is display1:inst3|lpm_divide:div_rtl_4|lpm_divide_5nf:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_se8:add_sub_12|add_sub_cella[1]~95 at LC_X16_Y9_N7
--operation mode is arithmetic

U9L5_cout_0 = !K2L74 & !K2L75 & !U9L8;
U9L5 = CARRY(U9L5_cout_0);

--U9L6 is display1:inst3|lpm_divide:div_rtl_4|lpm_divide_5nf:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_se8:add_sub_12|add_sub_cella[1]~95COUT1_141 at LC_X16_Y9_N7
--operation mode is arithmetic

U9L6_cout_1 = !K2L74 & !K2L75 & !U9L9;
U9L6 = CARRY(U9L6_cout_1);


--T2L6 is display1:inst3|lpm_divide:div_rtl_4|lpm_divide_5nf:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_re8:add_sub_7|add_sub_cella[1]~83 at LC_X12_Y10_N1
--operation mode is arithmetic

T2L6 = EB5L1 $ (T2L23);

--T2L7 is display1:inst3|lpm_divide:div_rtl_4|lpm_divide_5nf:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_re8:add_sub_7|add_sub_cella[1]~85 at LC_X12_Y10_N1
--operation mode is arithmetic

T2L7_cout_0 = !T2L23 # !EB5L1;
T2L7 = CARRY(T2L7_cout_0);

--T2L8 is display1:inst3|lpm_divide:div_rtl_4|lpm_divide_5nf:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_re8:add_sub_7|add_sub_cella[1]~85COUT1_123 at LC_X12_Y10_N1
--operation mode is arithmetic

T2L8_cout_1 = !T2L24 # !EB5L1;
T2L8 = CARRY(T2L8_cout_1);


--EB5L1 is display1:inst3|lpm_mult:mult_rtl_3|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~82 at LC_X12_Y7_N3
--operation mode is arithmetic

EB5L1 = AB2L4 $ AB2L7 $ EB5L15;

--EB5L2 is display1:inst3|lpm_mult:mult_rtl_3|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~84 at LC_X12_Y7_N3
--operation mode is arithmetic

EB5L2_cout_0 = AB2L4 & !AB2L7 & !EB5L15 # !AB2L4 & (!EB5L15 # !AB2L7);
EB5L2 = CARRY(EB5L2_cout_0);

--EB5L3 is display1:inst3|lpm_mult:mult_rtl_3|multcore:mult_core|mpar_add:padder|lpm_add_sub:adder[0]|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]~84COUT1 at LC_X12_Y7_N3
--operation mode is arithmetic

EB5L3_cout_1 = AB2L4 & !AB2L7 & !EB5L16 # !AB2L4 & (!EB5L16 # !AB2L7);
EB5L3 = CARRY(EB5L3_cout_1);


--U11L5 is display1:inst3|lpm_divide:div_rtl_4|lpm_divide_5nf:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_se8:add_sub_8|add_sub_cella[1]~88 at LC_X10_Y9_N8
--operation mode is normal

U11L5_carry_eqn = (!U11L13 & U11L20) # (U11L13 & U11L21);
U11L5 = !U11L5_carry_eqn;


--K2L22 is display1:inst3|lpm_divide:div_rtl_4|lpm_divide_5nf:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|StageOut[75]~2625 at LC_X12_Y9_N4
--operation mode is normal

K2L22 = !U11L5 & (T2L5 & T2L6 # !T2L5 & (EB5L1));


--U11L6 is display1:inst3|lpm_divide:div_rtl_4|lpm_divide_5nf:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_se8:add_sub_8|add_sub_cella[1]~93 at LC_X10_Y9_N2
--operation mode is arithmetic

U11L6 = U11L23 $ (!K2L4 & !K2L5);

--U11L7 is display1:inst3|lpm_divide:div_rtl_4|lpm_divide_5nf:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_se8:add_sub_8|add_sub_cella[1]~95 at LC_X10_Y9_N2
--operation mode is arithmetic

U11L7_cout_0 = !U11L23 & (K2L4 # K2L5);
U11L7 = CARRY(U11L7_cout_0);

--U11L8 is display1:inst3|lpm_divide:div_rtl_4|lpm_divide_5nf:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_se8:add_sub_8|add_sub_cella[1]~95COUT1_139 at LC_X10_Y9_N2
--operation mode is arithmetic

U11L8_cout_1 = !U11L24 & (K2L4 # K2L5);
U11L8 = CARRY(U11L8_cout_1);


--U12L5 is display1:inst3|lpm_divide:div_rtl_4|lpm_divide_5nf:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_se8:add_sub_9|add_sub_cella[1]~89 at LC_X11_Y10_N8
--operation mode is normal

U12L5_carry_eqn = (!U12L16 & U12L20) # (U12L16 & U12L21);
U12L5 = !U12L5_carry_eqn;


--K2L39 is display1:inst3|lpm_divide:div_rtl_4|lpm_divide_5nf:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|StageOut[85]~2626 at LC_X12_Y8_N5
--operation mode is normal

K2L39 = !U12L5 & (K2L22 # U11L6 & U11L5);