maxmin.fit.eqn

一个自己编写的这次2008北京市电子竞赛VHDL源程序

Q8L5 = !Q8L7;

--D1_segmin[6] is display1:inst3|segmin[6] at LC_X10_Y8_N4
--operation mode is normal

D1_segmin[6] = DFFEAS(Q8L5, GLOBAL(C1_clko), GLOBAL(en), , , , , , );


--Q9L5 is display1:inst3|lpm_divide:div_rtl_5|lpm_divide_klf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|add_sub_oe8:add_sub_6|add_sub_cella[2]~46 at LC_X10_Y7_N4
--operation mode is normal

Q9L5 = !Q9L7;

--D1_segmin[5] is display1:inst3|segmin[5] at LC_X10_Y7_N4
--operation mode is normal

D1_segmin[5] = DFFEAS(Q9L5, GLOBAL(C1_clko), GLOBAL(en), , , , , , );


--Q10L1 is display1:inst3|lpm_divide:div_rtl_5|lpm_divide_klf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|add_sub_oe8:add_sub_7|add_sub_cella[2]~46 at LC_X11_Y7_N4
--operation mode is normal

Q10L1 = !Q10L3;

--D1_segmin[4] is display1:inst3|segmin[4] at LC_X11_Y7_N4
--operation mode is normal

D1_segmin[4] = DFFEAS(Q10L1, GLOBAL(C1_clko), GLOBAL(en), , , , , , );


--D1L2 is display1:inst3|add~559 at LC_X11_Y7_N8
--operation mode is normal

D1L2 = Q10L1 $ Q8L5;


--U7L3 is display1:inst3|lpm_divide:div_rtl_4|lpm_divide_5nf:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_se8:add_sub_10|add_sub_cella[1]~89 at LC_X15_Y9_N8
--operation mode is normal

U7L3_carry_eqn = (!U7L8 & U7L5) # (U7L8 & U7L6);
U7L3 = !U7L3_carry_eqn;


--U8L3 is display1:inst3|lpm_divide:div_rtl_4|lpm_divide_5nf:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_se8:add_sub_11|add_sub_cella[1]~89 at LC_X15_Y8_N8
--operation mode is normal

U8L3_carry_eqn = (!U8L14 & U8L5) # (U8L14 & U8L6);
U8L3 = !U8L3_carry_eqn;


--U9L3 is display1:inst3|lpm_divide:div_rtl_4|lpm_divide_5nf:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_se8:add_sub_12|add_sub_cella[1]~88 at LC_X16_Y9_N8
--operation mode is normal

U9L3_carry_eqn = (!U9L14 & U9L5) # (U9L14 & U9L6);
U9L3 = !U9L3_carry_eqn;


--D1L23 is display1:inst3|segmin[0]~108COUT0 at LC_X12_Y8_N7
--operation mode is arithmetic

D1L23_cout_0 = K2L77 # K2L76;
D1L23 = CARRY(D1L23_cout_0);

--D1L24 is display1:inst3|segmin[0]~108COUT1 at LC_X12_Y8_N7
--operation mode is arithmetic

D1L24_cout_1 = K2L77 # K2L76;
D1L24 = CARRY(D1L24_cout_1);


--Q12_cout is display1:inst3|lpm_divide:div_rtl_8|lpm_divide_klf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|add_sub_oe8:add_sub_4|cout at LC_X11_Y4_N5
--operation mode is arithmetic

Q12_cout_cout_0 = Q12L5 & T3L5;
Q12_cout = CARRY(Q12_cout_cout_0);

--Q12L16 is display1:inst3|lpm_divide:div_rtl_8|lpm_divide_klf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|add_sub_oe8:add_sub_4|cout~COUT1 at LC_X11_Y4_N5
--operation mode is arithmetic

Q12L16_cout_1 = Q12L5 & T3L5;
Q12L16 = CARRY(Q12L16_cout_1);


--Q13L5 is display1:inst3|lpm_divide:div_rtl_8|lpm_divide_klf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|add_sub_oe8:add_sub_5|add_sub_cella[2]~46 at LC_X11_Y6_N4
--operation mode is normal

Q13L5 = !Q13L7;

--D1_segpp[6] is display1:inst3|segpp[6] at LC_X11_Y6_N4
--operation mode is normal

D1_segpp[6] = DFFEAS(Q13L5, GLOBAL(C1_clko), GLOBAL(en), , , , , , );


--Q14L5 is display1:inst3|lpm_divide:div_rtl_8|lpm_divide_klf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|add_sub_oe8:add_sub_6|add_sub_cella[2]~46 at LC_X12_Y6_N4
--operation mode is normal

Q14L5 = !Q14L7;

--D1_segpp[5] is display1:inst3|segpp[5] at LC_X12_Y6_N4
--operation mode is normal

D1_segpp[5] = DFFEAS(Q14L5, GLOBAL(C1_clko), GLOBAL(en), , , , , , );


--Q15L1 is display1:inst3|lpm_divide:div_rtl_8|lpm_divide_klf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|add_sub_oe8:add_sub_7|add_sub_cella[2]~46 at LC_X15_Y3_N9
--operation mode is normal

Q15L1 = !Q15L3;

--D1_segpp[4] is display1:inst3|segpp[4] at LC_X15_Y3_N9
--operation mode is normal

D1_segpp[4] = DFFEAS(Q15L1, GLOBAL(C1_clko), GLOBAL(en), , , , , , );


--D1L3 is display1:inst3|add~560 at LC_X15_Y3_N3
--operation mode is normal

D1L3 = Q15L1 $ Q13L5;


--U13L5 is display1:inst3|lpm_divide:div_rtl_7|lpm_divide_5nf:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_se8:add_sub_10|add_sub_cella[1]~89 at LC_X19_Y6_N8
--operation mode is normal

U13L5_carry_eqn = (!U13L10 & U13L7) # (U13L10 & U13L8);
U13L5 = !U13L5_carry_eqn;


--U14L5 is display1:inst3|lpm_divide:div_rtl_7|lpm_divide_5nf:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_se8:add_sub_11|add_sub_cella[1]~89 at LC_X16_Y6_N8
--operation mode is normal

U14L5_carry_eqn = (!U14L16 & U14L7) # (U14L16 & U14L8);
U14L5 = !U14L5_carry_eqn;


--U15L5 is display1:inst3|lpm_divide:div_rtl_7|lpm_divide_5nf:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_se8:add_sub_12|add_sub_cella[1]~88 at LC_X16_Y3_N8
--operation mode is normal

U15L5_carry_eqn = (!U15L16 & U15L7) # (U15L16 & U15L8);
U15L5 = !U15L5_carry_eqn;


--D1L39 is display1:inst3|segpp[0]~108COUT0 at LC_X20_Y6_N3
--operation mode is arithmetic

D1L39_cout_0 = K3L77 # K3L76;
D1L39 = CARRY(D1L39_cout_0);

--D1L40 is display1:inst3|segpp[0]~108COUT1 at LC_X20_Y6_N3
--operation mode is arithmetic

D1L40_cout_1 = K3L77 # K3L76;
D1L40 = CARRY(D1L40_cout_1);


--B1_clko is ADC0820:inst|clko at LC_X7_Y5_N5
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

B1_clko_lut_out = GND;
B1_clko = DFFEAS(B1_clko_lut_out, GLOBAL(clk), VCC, , , B1_i[4], , , VCC);


--B1_current_state_12 is ADC0820:inst|current_state_12 at LC_X26_Y6_N4
--operation mode is normal
--sload is tied to vcc, which is functionally the same as treating the sdata port as the data input.

B1_current_state_12_lut_out = GND;
B1_current_state_12 = DFFEAS(B1_current_state_12_lut_out, GLOBAL(B1_clko), VCC, , , B1_current_state.st4, , , VCC);


--B1_current_state_6 is ADC0820:inst|current_state_6 at LC_X26_Y6_N9
--operation mode is normal

B1_current_state_6_lut_out = B1_current_state.st1;
B1_current_state_6 = DFFEAS(B1_current_state_6_lut_out, GLOBAL(B1_clko), VCC, , , , , , );


--C1_i[16] is calculate:inst2|i[16] at LC_X9_Y6_N7
--operation mode is arithmetic

C1_i[16]_carry_eqn = (!C1L73 & C1L78) # (C1L73 & C1L79);
C1_i[16]_lut_out = C1_i[16] $ (!C1_i[16]_carry_eqn);
C1_i[16] = DFFEAS(C1_i[16]_lut_out, !GLOBAL(B1_current_state.st0), VCC, , , , , , );

--C1L81 is calculate:inst2|i[16]~131 at LC_X9_Y6_N7
--operation mode is arithmetic

C1L81_cout_0 = C1_i[16] & (!C1L78);
C1L81 = CARRY(C1L81_cout_0);

--C1L82 is calculate:inst2|i[16]~131COUT1_212 at LC_X9_Y6_N7
--operation mode is arithmetic

C1L82_cout_1 = C1_i[16] & (!C1L79);
C1L82 = CARRY(C1L82_cout_1);


--T1L5 is display1:inst3|lpm_divide:div_rtl_1|lpm_divide_5nf:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_re8:add_sub_7|add_sub_cella[1]~78 at LC_X21_Y9_N7
--operation mode is normal

T1L5_carry_eqn = (!T1L13 & T1L10) # (T1L13 & T1L11);
T1L5 = T1L5_carry_eqn;


--Q2L5 is display1:inst3|lpm_divide:div_rtl_2|lpm_divide_klf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|add_sub_oe8:add_sub_4|add_sub_cella[2]~48 at LC_X22_Y7_N3
--operation mode is normal

Q2L5 = !Q2L7;


--Q3L7 is display1:inst3|lpm_divide:div_rtl_2|lpm_divide_klf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|add_sub_oe8:add_sub_5|add_sub_cella[2]~53 at LC_X23_Y7_N3
--operation mode is arithmetic

Q3L7_cout_0 = !Y1L5 & !Y1L6 & !Q3L10;
Q3L7 = CARRY(Q3L7_cout_0);

--Q3L8 is display1:inst3|lpm_divide:div_rtl_2|lpm_divide_klf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|add_sub_oe8:add_sub_5|add_sub_cella[2]~53COUT1_77 at LC_X23_Y7_N3
--operation mode is arithmetic

Q3L8_cout_1 = !Y1L5 & !Y1L6 & !Q3L11;
Q3L8 = CARRY(Q3L8_cout_1);


--Q4L7 is display1:inst3|lpm_divide:div_rtl_2|lpm_divide_klf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|add_sub_oe8:add_sub_6|add_sub_cella[2]~53 at LC_X25_Y7_N3
--operation mode is arithmetic

Q4L7_cout_0 = !Y1L11 & !Y1L12 & !Q4L10;
Q4L7 = CARRY(Q4L7_cout_0);

--Q4L8 is display1:inst3|lpm_divide:div_rtl_2|lpm_divide_klf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|add_sub_oe8:add_sub_6|add_sub_cella[2]~53COUT1_77 at LC_X25_Y7_N3
--operation mode is arithmetic

Q4L8_cout_1 = !Y1L11 & !Y1L12 & !Q4L11;
Q4L8 = CARRY(Q4L8_cout_1);


--Q5L3 is display1:inst3|lpm_divide:div_rtl_2|lpm_divide_klf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|add_sub_oe8:add_sub_7|add_sub_cella[2]~53 at LC_X25_Y8_N8
--operation mode is arithmetic

Q5L3_cout_0 = !Y1L19 & !Y1L20 & !Q5L6;
Q5L3 = CARRY(Q5L3_cout_0);

--Q5L4 is display1:inst3|lpm_divide:div_rtl_2|lpm_divide_klf:auto_generated|sign_div_unsign_mhg:divider|alt_u_div_hld:divider|add_sub_oe8:add_sub_7|add_sub_cella[2]~53COUT1_74 at LC_X25_Y8_N8
--operation mode is arithmetic

Q5L4_cout_1 = !Y1L19 & !Y1L20 & !Q5L7;
Q5L4 = CARRY(Q5L4_cout_1);


--U1L5 is display1:inst3|lpm_divide:div_rtl_1|lpm_divide_5nf:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_se8:add_sub_10|add_sub_cella[1]~96 at LC_X22_Y11_N7
--operation mode is arithmetic

U1L5_cout_0 = !K1L44 & !K1L45 & !U1L12;
U1L5 = CARRY(U1L5_cout_0);

--U1L6 is display1:inst3|lpm_divide:div_rtl_1|lpm_divide_5nf:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_se8:add_sub_10|add_sub_cella[1]~96COUT1_142 at LC_X22_Y11_N7
--operation mode is arithmetic

U1L6_cout_1 = !K1L44 & !K1L45 & !U1L13;
U1L6 = CARRY(U1L6_cout_1);


--U2L5 is display1:inst3|lpm_divide:div_rtl_1|lpm_divide_5nf:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_se8:add_sub_11|add_sub_cella[1]~96 at LC_X24_Y9_N7
--operation mode is arithmetic

U2L5_cout_0 = !K1L60 & !K1L61 & !U2L11;
U2L5 = CARRY(U2L5_cout_0);

--U2L6 is display1:inst3|lpm_divide:div_rtl_1|lpm_divide_5nf:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_se8:add_sub_11|add_sub_cella[1]~96COUT1_142 at LC_X24_Y9_N7
--operation mode is arithmetic

U2L6_cout_1 = !K1L60 & !K1L61 & !U2L12;
U2L6 = CARRY(U2L6_cout_1);


--U3L5 is display1:inst3|lpm_divide:div_rtl_1|lpm_divide_5nf:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_se8:add_sub_12|add_sub_cella[1]~95 at LC_X24_Y8_N7
--operation mode is arithmetic

U3L5_cout_0 = !K1L75 & !K1L76 & !U3L8;
U3L5 = CARRY(U3L5_cout_0);

--U3L6 is display1:inst3|lpm_divide:div_rtl_1|lpm_divide_5nf:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_se8:add_sub_12|add_sub_cella[1]~95COUT1_141 at LC_X24_Y8_N7
--operation mode is arithmetic

U3L6_cout_1 = !K1L75 & !K1L76 & !U3L9;
U3L6 = CARRY(U3L6_cout_1);


--U1L7 is display1:inst3|lpm_divide:div_rtl_1|lpm_divide_5nf:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_se8:add_sub_10|add_sub_cella[1]~99 at LC_X22_Y11_N4
--operation mode is arithmetic

U1L7 = U1L18 $ (!K1L38 & !K1L39);

--U1L8 is display1:inst3|lpm_divide:div_rtl_1|lpm_divide_5nf:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_se8:add_sub_10|add_sub_cella[1]~101 at LC_X22_Y11_N4
--operation mode is arithmetic

U1L8 = U1L9;


--U6L5 is display1:inst3|lpm_divide:div_rtl_1|lpm_divide_5nf:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_se8:add_sub_9|add_sub_cella[1]~89 at LC_X22_Y10_N3
--operation mode is arithmetic

U6L5 = U6L20 $ (K1L22 # K1L21);

--U6L6 is display1:inst3|lpm_divide:div_rtl_1|lpm_divide_5nf:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_se8:add_sub_9|add_sub_cella[1]~91 at LC_X22_Y10_N3
--operation mode is arithmetic

U6L6_cout_0 = !K1L22 & !K1L21 # !U6L20;
U6L6 = CARRY(U6L6_cout_0);

--U6L7 is display1:inst3|lpm_divide:div_rtl_1|lpm_divide_5nf:auto_generated|sign_div_unsign_7jg:divider|alt_u_div_jod:divider|add_sub_se8:add_sub_9|add_sub_cella[1]~91COUT1 at LC_X22_Y10_N3
--operation mode is arithmetic