cpu.map.eqn

来自「实现了CPU的基本功能」· EQN 代码 · 共 2,251 行 · 第 1/5 页

-- Copyright (C) 1991-2005 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files any of the foregoing 
-- (including device programming or simulation files), and any 
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-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.
--B1_temp_acc[15] is ALU:inst|temp_acc[15]
--operation mode is normal

B1_temp_acc[15]_lut_out = B1L126 # B1_temp_acc[15] & B1L98 # !B1L129;
B1_temp_acc[15] = DFFEA(B1_temp_acc[15]_lut_out, CLOCK, !RESET, , , , );

--B1L594Q is ALU:inst|temp_acc[15]~760
--operation mode is normal

B1L594Q = B1_temp_acc[15];


--B1_temp_acc[14] is ALU:inst|temp_acc[14]
--operation mode is normal

B1_temp_acc[14]_lut_out = B1L136 # B1_temp_acc[14] & B1L98 # !B1L129;
B1_temp_acc[14] = DFFEA(B1_temp_acc[14]_lut_out, CLOCK, !RESET, , , , );

--B1L592Q is ALU:inst|temp_acc[14]~761
--operation mode is normal

B1L592Q = B1_temp_acc[14];


--B1_temp_acc[13] is ALU:inst|temp_acc[13]
--operation mode is normal

B1_temp_acc[13]_lut_out = B1L139 # B1_temp_acc[13] & B1L98 # !B1L319;
B1_temp_acc[13] = DFFEA(B1_temp_acc[13]_lut_out, CLOCK, !RESET, , , , );

--B1L590Q is ALU:inst|temp_acc[13]~762
--operation mode is normal

B1L590Q = B1_temp_acc[13];


--B1_temp_acc[12] is ALU:inst|temp_acc[12]
--operation mode is normal

B1_temp_acc[12]_lut_out = B1L141 # B1_temp_acc[12] & B1L98 # !B1L320;
B1_temp_acc[12] = DFFEA(B1_temp_acc[12]_lut_out, CLOCK, !RESET, , , , );

--B1L588Q is ALU:inst|temp_acc[12]~763
--operation mode is normal

B1L588Q = B1_temp_acc[12];


--B1_temp_acc[11] is ALU:inst|temp_acc[11]
--operation mode is normal

B1_temp_acc[11]_lut_out = B1L143 # B1_temp_acc[11] & B1L98 # !B1L321;
B1_temp_acc[11] = DFFEA(B1_temp_acc[11]_lut_out, CLOCK, !RESET, , , , );

--B1L586Q is ALU:inst|temp_acc[11]~764
--operation mode is normal

B1L586Q = B1_temp_acc[11];


--B1_temp_acc[10] is ALU:inst|temp_acc[10]
--operation mode is normal

B1_temp_acc[10]_lut_out = B1L145 # B1_temp_acc[10] & B1L98 # !B1L322;
B1_temp_acc[10] = DFFEA(B1_temp_acc[10]_lut_out, CLOCK, !RESET, , , , );

--B1L584Q is ALU:inst|temp_acc[10]~765
--operation mode is normal

B1L584Q = B1_temp_acc[10];


--B1_temp_acc[9] is ALU:inst|temp_acc[9]
--operation mode is normal

B1_temp_acc[9]_lut_out = B1L147 # B1_temp_acc[9] & B1L98 # !B1L323;
B1_temp_acc[9] = DFFEA(B1_temp_acc[9]_lut_out, CLOCK, !RESET, , , , );

--B1L582Q is ALU:inst|temp_acc[9]~766
--operation mode is normal

B1L582Q = B1_temp_acc[9];


--B1_temp_acc[8] is ALU:inst|temp_acc[8]
--operation mode is normal

B1_temp_acc[8]_lut_out = B1L149 # B1_temp_acc[8] & B1L98 # !B1L324;
B1_temp_acc[8] = DFFEA(B1_temp_acc[8]_lut_out, CLOCK, !RESET, , , , );

--B1L580Q is ALU:inst|temp_acc[8]~767
--operation mode is normal

B1L580Q = B1_temp_acc[8];


--B1_temp_acc[7] is ALU:inst|temp_acc[7]
--operation mode is normal

B1_temp_acc[7]_lut_out = B1L151 # B1_temp_acc[7] & B1L98 # !B1L325;
B1_temp_acc[7] = DFFEA(B1_temp_acc[7]_lut_out, CLOCK, !RESET, , , , );

--B1L578Q is ALU:inst|temp_acc[7]~768
--operation mode is normal

B1L578Q = B1_temp_acc[7];


--B1_temp_acc[6] is ALU:inst|temp_acc[6]
--operation mode is normal

B1_temp_acc[6]_lut_out = B1L153 # B1_temp_acc[6] & B1L98 # !B1L326;
B1_temp_acc[6] = DFFEA(B1_temp_acc[6]_lut_out, CLOCK, !RESET, , , , );

--B1L576Q is ALU:inst|temp_acc[6]~769
--operation mode is normal

B1L576Q = B1_temp_acc[6];


--B1_temp_acc[5] is ALU:inst|temp_acc[5]
--operation mode is normal

B1_temp_acc[5]_lut_out = B1L155 # B1_temp_acc[5] & B1L98 # !B1L327;
B1_temp_acc[5] = DFFEA(B1_temp_acc[5]_lut_out, CLOCK, !RESET, , , , );

--B1L574Q is ALU:inst|temp_acc[5]~770
--operation mode is normal

B1L574Q = B1_temp_acc[5];


--B1_temp_acc[4] is ALU:inst|temp_acc[4]
--operation mode is normal

B1_temp_acc[4]_lut_out = B1L157 # B1_temp_acc[4] & B1L98 # !B1L328;
B1_temp_acc[4] = DFFEA(B1_temp_acc[4]_lut_out, CLOCK, !RESET, , , , );

--B1L572Q is ALU:inst|temp_acc[4]~771
--operation mode is normal

B1L572Q = B1_temp_acc[4];


--B1_temp_acc[3] is ALU:inst|temp_acc[3]
--operation mode is normal

B1_temp_acc[3]_lut_out = B1L159 # B1_temp_acc[3] & B1L98 # !B1L329;
B1_temp_acc[3] = DFFEA(B1_temp_acc[3]_lut_out, CLOCK, !RESET, , , , );

--B1L570Q is ALU:inst|temp_acc[3]~772
--operation mode is normal

B1L570Q = B1_temp_acc[3];


--B1_temp_acc[2] is ALU:inst|temp_acc[2]
--operation mode is normal

B1_temp_acc[2]_lut_out = B1L161 # B1_temp_acc[2] & B1L98 # !B1L330;
B1_temp_acc[2] = DFFEA(B1_temp_acc[2]_lut_out, CLOCK, !RESET, , , , );

--B1L568Q is ALU:inst|temp_acc[2]~773
--operation mode is normal

B1L568Q = B1_temp_acc[2];


--B1_temp_acc[1] is ALU:inst|temp_acc[1]
--operation mode is normal

B1_temp_acc[1]_lut_out = B1L163 # B1_temp_acc[1] & B1L98 # !B1L331;
B1_temp_acc[1] = DFFEA(B1_temp_acc[1]_lut_out, CLOCK, !RESET, , , , );

--B1L566Q is ALU:inst|temp_acc[1]~774
--operation mode is normal

B1L566Q = B1_temp_acc[1];


--B1_temp_acc[0] is ALU:inst|temp_acc[0]
--operation mode is normal

B1_temp_acc[0]_lut_out = B1L167 # B1_temp_acc[0] & B1L98 # !B1L332;
B1_temp_acc[0] = DFFEA(B1_temp_acc[0]_lut_out, CLOCK, !RESET, , , , );

--B1L564Q is ALU:inst|temp_acc[0]~775
--operation mode is normal

B1L564Q = B1_temp_acc[0];


--V1_q[25] is rom:inst24|lpm_rom:lpm_rom_component|altrom:srom|q[25]
V1_q[25]_write_address = WR_ADDR(J1_CAR[0], J1_CAR[1], J1_CAR[2], J1_CAR[3], J1_CAR[4], J1_CAR[5], J1_CAR[6], J1_CAR[7]);
V1_q[25]_read_address = RD_ADDR(J1_CAR[0], J1_CAR[1], J1_CAR[2], J1_CAR[3], J1_CAR[4], J1_CAR[5], J1_CAR[6], J1_CAR[7]);
V1_q[25] = MEMORY_SEGMENT(, , , , , , , , V1_q[25]_write_address, V1_q[25]_read_address);


--V1_q[24] is rom:inst24|lpm_rom:lpm_rom_component|altrom:srom|q[24]
V1_q[24]_write_address = WR_ADDR(J1_CAR[0], J1_CAR[1], J1_CAR[2], J1_CAR[3], J1_CAR[4], J1_CAR[5], J1_CAR[6], J1_CAR[7]);
V1_q[24]_read_address = RD_ADDR(J1_CAR[0], J1_CAR[1], J1_CAR[2], J1_CAR[3], J1_CAR[4], J1_CAR[5], J1_CAR[6], J1_CAR[7]);
V1_q[24] = MEMORY_SEGMENT(, , , , , , , , V1_q[24]_write_address, V1_q[24]_read_address);


--V1_q[23] is rom:inst24|lpm_rom:lpm_rom_component|altrom:srom|q[23]
V1_q[23]_write_address = WR_ADDR(J1_CAR[0], J1_CAR[1], J1_CAR[2], J1_CAR[3], J1_CAR[4], J1_CAR[5], J1_CAR[6], J1_CAR[7]);
V1_q[23]_read_address = RD_ADDR(J1_CAR[0], J1_CAR[1], J1_CAR[2], J1_CAR[3], J1_CAR[4], J1_CAR[5], J1_CAR[6], J1_CAR[7]);
V1_q[23] = MEMORY_SEGMENT(, , , , , , , , V1_q[23]_write_address, V1_q[23]_read_address);


--V1_q[22] is rom:inst24|lpm_rom:lpm_rom_component|altrom:srom|q[22]
V1_q[22]_write_address = WR_ADDR(J1_CAR[0], J1_CAR[1], J1_CAR[2], J1_CAR[3], J1_CAR[4], J1_CAR[5], J1_CAR[6], J1_CAR[7]);
V1_q[22]_read_address = RD_ADDR(J1_CAR[0], J1_CAR[1], J1_CAR[2], J1_CAR[3], J1_CAR[4], J1_CAR[5], J1_CAR[6], J1_CAR[7]);
V1_q[22] = MEMORY_SEGMENT(, , , , , , , , V1_q[22]_write_address, V1_q[22]_read_address);


--V1_q[21] is rom:inst24|lpm_rom:lpm_rom_component|altrom:srom|q[21]
V1_q[21]_write_address = WR_ADDR(J1_CAR[0], J1_CAR[1], J1_CAR[2], J1_CAR[3], J1_CAR[4], J1_CAR[5], J1_CAR[6], J1_CAR[7]);
V1_q[21]_read_address = RD_ADDR(J1_CAR[0], J1_CAR[1], J1_CAR[2], J1_CAR[3], J1_CAR[4], J1_CAR[5], J1_CAR[6], J1_CAR[7]);
V1_q[21] = MEMORY_SEGMENT(, , , , , , , , V1_q[21]_write_address, V1_q[21]_read_address);


--V1_q[20] is rom:inst24|lpm_rom:lpm_rom_component|altrom:srom|q[20]
V1_q[20]_write_address = WR_ADDR(J1_CAR[0], J1_CAR[1], J1_CAR[2], J1_CAR[3], J1_CAR[4], J1_CAR[5], J1_CAR[6], J1_CAR[7]);
V1_q[20]_read_address = RD_ADDR(J1_CAR[0], J1_CAR[1], J1_CAR[2], J1_CAR[3], J1_CAR[4], J1_CAR[5], J1_CAR[6], J1_CAR[7]);
V1_q[20] = MEMORY_SEGMENT(, , , , , , , , V1_q[20]_write_address, V1_q[20]_read_address);


--V1_q[19] is rom:inst24|lpm_rom:lpm_rom_component|altrom:srom|q[19]
V1_q[19]_write_address = WR_ADDR(J1_CAR[0], J1_CAR[1], J1_CAR[2], J1_CAR[3], J1_CAR[4], J1_CAR[5], J1_CAR[6], J1_CAR[7]);
V1_q[19]_read_address = RD_ADDR(J1_CAR[0], J1_CAR[1], J1_CAR[2], J1_CAR[3], J1_CAR[4], J1_CAR[5], J1_CAR[6], J1_CAR[7]);
V1_q[19] = MEMORY_SEGMENT(, , , , , , , , V1_q[19]_write_address, V1_q[19]_read_address);


--V1_q[18] is rom:inst24|lpm_rom:lpm_rom_component|altrom:srom|q[18]
V1_q[18]_write_address = WR_ADDR(J1_CAR[0], J1_CAR[1], J1_CAR[2], J1_CAR[3], J1_CAR[4], J1_CAR[5], J1_CAR[6], J1_CAR[7]);
V1_q[18]_read_address = RD_ADDR(J1_CAR[0], J1_CAR[1], J1_CAR[2], J1_CAR[3], J1_CAR[4], J1_CAR[5], J1_CAR[6], J1_CAR[7]);
V1_q[18] = MEMORY_SEGMENT(, , , , , , , , V1_q[18]_write_address, V1_q[18]_read_address);


--V1_q[17] is rom:inst24|lpm_rom:lpm_rom_component|altrom:srom|q[17]
V1_q[17]_write_address = WR_ADDR(J1_CAR[0], J1_CAR[1], J1_CAR[2], J1_CAR[3], J1_CAR[4], J1_CAR[5], J1_CAR[6], J1_CAR[7]);
V1_q[17]_read_address = RD_ADDR(J1_CAR[0], J1_CAR[1], J1_CAR[2], J1_CAR[3], J1_CAR[4], J1_CAR[5], J1_CAR[6], J1_CAR[7]);
V1_q[17] = MEMORY_SEGMENT(, , , , , , , , V1_q[17]_write_address, V1_q[17]_read_address);


--V1_q[16] is rom:inst24|lpm_rom:lpm_rom_component|altrom:srom|q[16]
V1_q[16]_write_address = WR_ADDR(J1_CAR[0], J1_CAR[1], J1_CAR[2], J1_CAR[3], J1_CAR[4], J1_CAR[5], J1_CAR[6], J1_CAR[7]);
V1_q[16]_read_address = RD_ADDR(J1_CAR[0], J1_CAR[1], J1_CAR[2], J1_CAR[3], J1_CAR[4], J1_CAR[5], J1_CAR[6], J1_CAR[7]);
V1_q[16] = MEMORY_SEGMENT(, , , , , , , , V1_q[16]_write_address, V1_q[16]_read_address);


--V1_q[15] is rom:inst24|lpm_rom:lpm_rom_component|altrom:srom|q[15]
V1_q[15]_write_address = WR_ADDR(J1_CAR[0], J1_CAR[1], J1_CAR[2], J1_CAR[3], J1_CAR[4], J1_CAR[5], J1_CAR[6], J1_CAR[7]);
V1_q[15]_read_address = RD_ADDR(J1_CAR[0], J1_CAR[1], J1_CAR[2], J1_CAR[3], J1_CAR[4], J1_CAR[5], J1_CAR[6], J1_CAR[7]);
V1_q[15] = MEMORY_SEGMENT(, , , , , , , , V1_q[15]_write_address, V1_q[15]_read_address);


--V1_q[14] is rom:inst24|lpm_rom:lpm_rom_component|altrom:srom|q[14]
V1_q[14]_write_address = WR_ADDR(J1_CAR[0], J1_CAR[1], J1_CAR[2], J1_CAR[3], J1_CAR[4], J1_CAR[5], J1_CAR[6], J1_CAR[7]);
V1_q[14]_read_address = RD_ADDR(J1_CAR[0], J1_CAR[1], J1_CAR[2], J1_CAR[3], J1_CAR[4], J1_CAR[5], J1_CAR[6], J1_CAR[7]);
V1_q[14] = MEMORY_SEGMENT(, , , , , , , , V1_q[14]_write_address, V1_q[14]_read_address);


--V1_q[13] is rom:inst24|lpm_rom:lpm_rom_component|altrom:srom|q[13]
V1_q[13]_write_address = WR_ADDR(J1_CAR[0], J1_CAR[1], J1_CAR[2], J1_CAR[3], J1_CAR[4], J1_CAR[5], J1_CAR[6], J1_CAR[7]);
V1_q[13]_read_address = RD_ADDR(J1_CAR[0], J1_CAR[1], J1_CAR[2], J1_CAR[3], J1_CAR[4], J1_CAR[5], J1_CAR[6], J1_CAR[7]);
V1_q[13] = MEMORY_SEGMENT(, , , , , , , , V1_q[13]_write_address, V1_q[13]_read_address);


--V1_q[12] is rom:inst24|lpm_rom:lpm_rom_component|altrom:srom|q[12]
V1_q[12]_write_address = WR_ADDR(J1_CAR[0], J1_CAR[1], J1_CAR[2], J1_CAR[3], J1_CAR[4], J1_CAR[5], J1_CAR[6], J1_CAR[7]);
V1_q[12]_read_address = RD_ADDR(J1_CAR[0], J1_CAR[1], J1_CAR[2], J1_CAR[3], J1_CAR[4], J1_CAR[5], J1_CAR[6], J1_CAR[7]);
V1_q[12] = MEMORY_SEGMENT(, , , , , , , , V1_q[12]_write_address, V1_q[12]_read_address);


--V1_q[11] is rom:inst24|lpm_rom:lpm_rom_component|altrom:srom|q[11]
V1_q[11]_write_address = WR_ADDR(J1_CAR[0], J1_CAR[1], J1_CAR[2], J1_CAR[3], J1_CAR[4], J1_CAR[5], J1_CAR[6], J1_CAR[7]);
V1_q[11]_read_address = RD_ADDR(J1_CAR[0], J1_CAR[1], J1_CAR[2], J1_CAR[3], J1_CAR[4], J1_CAR[5], J1_CAR[6], J1_CAR[7]);
V1_q[11] = MEMORY_SEGMENT(, , , , , , , , V1_q[11]_write_address, V1_q[11]_read_address);


--V1_q[10] is rom:inst24|lpm_rom:lpm_rom_component|altrom:srom|q[10]
V1_q[10]_write_address = WR_ADDR(J1_CAR[0], J1_CAR[1], J1_CAR[2], J1_CAR[3], J1_CAR[4], J1_CAR[5], J1_CAR[6], J1_CAR[7]);
V1_q[10]_read_address = RD_ADDR(J1_CAR[0], J1_CAR[1], J1_CAR[2], J1_CAR[3], J1_CAR[4], J1_CAR[5], J1_CAR[6], J1_CAR[7]);
V1_q[10] = MEMORY_SEGMENT(, , , , , , , , V1_q[10]_write_address, V1_q[10]_read_address);


--V1_q[9] is rom:inst24|lpm_rom:lpm_rom_component|altrom:srom|q[9]
V1_q[9]_write_address = WR_ADDR(J1_CAR[0], J1_CAR[1], J1_CAR[2], J1_CAR[3], J1_CAR[4], J1_CAR[5], J1_CAR[6], J1_CAR[7]);
V1_q[9]_read_address = RD_ADDR(J1_CAR[0], J1_CAR[1], J1_CAR[2], J1_CAR[3], J1_CAR[4], J1_CAR[5], J1_CAR[6], J1_CAR[7]);
V1_q[9] = MEMORY_SEGMENT(, , , , , , , , V1_q[9]_write_address, V1_q[9]_read_address);


--V1_q[8] is rom:inst24|lpm_rom:lpm_rom_component|altrom:srom|q[8]
V1_q[8]_write_address = WR_ADDR(J1_CAR[0], J1_CAR[1], J1_CAR[2], J1_CAR[3], J1_CAR[4], J1_CAR[5], J1_CAR[6], J1_CAR[7]);
V1_q[8]_read_address = RD_ADDR(J1_CAR[0], J1_CAR[1], J1_CAR[2], J1_CAR[3], J1_CAR[4], J1_CAR[5], J1_CAR[6], J1_CAR[7]);
V1_q[8] = MEMORY_SEGMENT(, , , , , , , , V1_q[8]_write_address, V1_q[8]_read_address);


--V1_q[7] is rom:inst24|lpm_rom:lpm_rom_component|altrom:srom|q[7]
V1_q[7]_write_address = WR_ADDR(J1_CAR[0], J1_CAR[1], J1_CAR[2], J1_CAR[3], J1_CAR[4], J1_CAR[5], J1_CAR[6], J1_CAR[7]);
V1_q[7]_read_address = RD_ADDR(J1_CAR[0], J1_CAR[1], J1_CAR[2], J1_CAR[3], J1_CAR[4], J1_CAR[5], J1_CAR[6], J1_CAR[7]);
V1_q[7] = MEMORY_SEGMENT(, , , , , , , , V1_q[7]_write_address, V1_q[7]_read_address);


--V1_q[6] is rom:inst24|lpm_rom:lpm_rom_component|altrom:srom|q[6]
V1_q[6]_write_address = WR_ADDR(J1_CAR[0], J1_CAR[1], J1_CAR[2], J1_CAR[3], J1_CAR[4], J1_CAR[5], J1_CAR[6], J1_CAR[7]);
V1_q[6]_read_address = RD_ADDR(J1_CAR[0], J1_CAR[1], J1_CAR[2], J1_CAR[3], J1_CAR[4], J1_CAR[5], J1_CAR[6], J1_CAR[7]);
V1_q[6] = MEMORY_SEGMENT(, , , , , , , , V1_q[6]_write_address, V1_q[6]_read_address);


--V1_q[5] is rom:inst24|lpm_rom:lpm_rom_component|altrom:srom|q[5]
V1_q[5]_write_address = WR_ADDR(J1_CAR[0], J1_CAR[1], J1_CAR[2], J1_CAR[3], J1_CAR[4], J1_CAR[5], J1_CAR[6], J1_CAR[7]);
V1_q[5]_read_address = RD_ADDR(J1_CAR[0], J1_CAR[1], J1_CAR[2], J1_CAR[3], J1_CAR[4], J1_CAR[5], J1_CAR[6], J1_CAR[7]);
V1_q[5] = MEMORY_SEGMENT(, , , , , , , , V1_q[5]_write_address, V1_q[5]_read_address);


--V1_q[4] is rom:inst24|lpm_rom:lpm_rom_component|altrom:srom|q[4]
V1_q[4]_write_address = WR_ADDR(J1_CAR[0], J1_CAR[1], J1_CAR[2], J1_CAR[3], J1_CAR[4], J1_CAR[5], J1_CAR[6], J1_CAR[7]);
V1_q[4]_read_address = RD_ADDR(J1_CAR[0], J1_CAR[1], J1_CAR[2], J1_CAR[3], J1_CAR[4], J1_CAR[5], J1_CAR[6], J1_CAR[7]);
V1_q[4] = MEMORY_SEGMENT(, , , , , , , , V1_q[4]_write_address, V1_q[4]_read_address);


--V1_q[3] is rom:inst24|lpm_rom:lpm_rom_component|altrom:srom|q[3]
V1_q[3]_write_address = WR_ADDR(J1_CAR[0], J1_CAR[1], J1_CAR[2], J1_CAR[3], J1_CAR[4], J1_CAR[5], J1_CAR[6], J1_CAR[7]);
V1_q[3]_read_address = RD_ADDR(J1_CAR[0], J1_CAR[1], J1_CAR[2], J1_CAR[3], J1_CAR[4], J1_CAR[5], J1_CAR[6], J1_CAR[7]);
V1_q[3] = MEMORY_SEGMENT(, , , , , , , , V1_q[3]_write_address, V1_q[3]_read_address);


--V1_q[2] is rom:inst24|lpm_rom:lpm_rom_component|altrom:srom|q[2]
V1_q[2]_write_address = WR_ADDR(J1_CAR[0], J1_CAR[1], J1_CAR[2], J1_CAR[3], J1_CAR[4], J1_CAR[5], J1_CAR[6], J1_CAR[7]);
V1_q[2]_read_address = RD_ADDR(J1_CAR[0], J1_CAR[1], J1_CAR[2], J1_CAR[3], J1_CAR[4], J1_CAR[5], J1_CAR[6], J1_CAR[7]);
V1_q[2] = MEMORY_SEGMENT(, , , , , , , , V1_q[2]_write_address, V1_q[2]_read_address);


--V1_q[1] is rom:inst24|lpm_rom:lpm_rom_component|altrom:srom|q[1]
V1_q[1]_write_address = WR_ADDR(J1_CAR[0], J1_CAR[1], J1_CAR[2], J1_CAR[3], J1_CAR[4], J1_CAR[5], J1_CAR[6], J1_CAR[7]);
V1_q[1]_read_address = RD_ADDR(J1_CAR[0], J1_CAR[1], J1_CAR[2], J1_CAR[3], J1_CAR[4], J1_CAR[5], J1_CAR[6], J1_CAR[7]);
V1_q[1] = MEMORY_SEGMENT(, , , , , , , , V1_q[1]_write_address, V1_q[1]_read_address);


--V1_q[0] is rom:inst24|lpm_rom:lpm_rom_component|altrom:srom|q[0]
V1_q[0]_write_address = WR_ADDR(J1_CAR[0], J1_CAR[1], J1_CAR[2], J1_CAR[3], J1_CAR[4], J1_CAR[5], J1_CAR[6], J1_CAR[7]);
V1_q[0]_read_address = RD_ADDR(J1_CAR[0], J1_CAR[1], J1_CAR[2], J1_CAR[3], J1_CAR[4], J1_CAR[5], J1_CAR[6], J1_CAR[7]);
V1_q[0] = MEMORY_SEGMENT(, , , , , , , , V1_q[0]_write_address, V1_q[0]_read_address);


--J1_CAR[7] is sequence:inst23|CAR[7]
--operation mode is normal

J1_CAR[7]_lut_out = M4_unreg_res_node[7] & (J1L31 # J1_CAR[7] & J1L30) # !M4_unreg_res_node[7] & J1_CAR[7] & J1L30;
J1_CAR[7] = DFFEA(J1_CAR[7]_lut_out, CLOCK, !RESET, , , , );

--J1L17Q is sequence:inst23|CAR[7]~278
--operation mode is normal

J1L17Q = J1_CAR[7];


--J1_CAR[6] is sequence:inst23|CAR[6]
--operation mode is normal

J1_CAR[6]_lut_out = J1L31 & (P11_cs_buffer[6] # J1_CAR[6] & J1L30) # !J1L31 & J1_CAR[6] & J1L30;
J1_CAR[6] = DFFEA(J1_CAR[6]_lut_out, CLOCK, !RESET, , , , );

--J1L15Q is sequence:inst23|CAR[6]~279
--operation mode is normal

J1L15Q = J1_CAR[6];


--J1_CAR[5] is sequence:inst23|CAR[5]
--operation mode is normal

J1_CAR[5]_lut_out = !J1L67;
J1_CAR[5] = DFFEA(J1_CAR[5]_lut_out, CLOCK, !RESET, , , , );

--J1L13Q is sequence:inst23|CAR[5]~280
--operation mode is normal

J1L13Q = J1_CAR[5];


--J1_CAR[4] is sequence:inst23|CAR[4]
--operation mode is normal

J1_CAR[4]_lut_out = J1L36 # J1L37 & (J1L39 # !J1L29);
J1_CAR[4] = DFFEA(J1_CAR[4]_lut_out, CLOCK, !RESET, , , , );

--J1L11Q is sequence:inst23|CAR[4]~281
--operation mode is normal

J1L11Q = J1_CAR[4];


--J1_CAR[3] is sequence:inst23|CAR[3]
--operation mode is normal

J1_CAR[3]_lut_out = J1L40 # J1L41 & J1L44;
J1_CAR[3] = DFFEA(J1_CAR[3]_lut_out, CLOCK, !RESET, , , , );

--J1L9Q is sequence:inst23|CAR[3]~282
--operation mode is normal

J1L9Q = J1_CAR[3];


--J1_CAR[2] is sequence:inst23|CAR[2]
--operation mode is normal

J1_CAR[2]_lut_out = J1L46 # J1L51 # J1L31 & P11_cs_buffer[2];
J1_CAR[2] = DFFEA(J1_CAR[2]_lut_out, CLOCK, !RESET, , , , );

--J1L7Q is sequence:inst23|CAR[2]~283
--operation mode is normal

J1L7Q = J1_CAR[2];


--J1_CAR[1] is sequence:inst23|CAR[1]
--operation mode is normal

J1_CAR[1]_lut_out = J1L32 & (J1L55 # J1L19 & !J1L29) # !J1L32 & (J1L19 & !J1L29);
J1_CAR[1] = DFFEA(J1_CAR[1]_lut_out, CLOCK, !RESET, , , , );

--J1L5Q is sequence:inst23|CAR[1]~284
--operation mode is normal

J1L5Q = J1_CAR[1];


--J1_CAR[0] is sequence:inst23|CAR[0]
--operation mode is arithmetic

J1_CAR[0]_lut_out = !J1L68;
J1_CAR[0] = DFFEA(J1_CAR[0]_lut_out, CLOCK, !RESET, , , , );