cpu.hier_info

来自「实现了CPU的基本功能」· HIER_INFO 代码 · 共 2,023 行 · 第 1/5 页

reset => output[10]~reg0.ACLR
reset => output[9]~reg0.ACLR
reset => output[8]~reg0.ACLR
reset => output[7]~reg0.ACLR
reset => output[6]~reg0.ACLR
reset => output[5]~reg0.ACLR
reset => output[4]~reg0.ACLR
reset => output[3]~reg0.ACLR
reset => output[2]~reg0.ACLR
reset => output[1]~reg0.ACLR
reset => output[0]~reg0.ACLR
reset => output[15]~reg0.ACLR
clk => output[14]~reg0.CLK
clk => output[13]~reg0.CLK
clk => output[12]~reg0.CLK
clk => output[11]~reg0.CLK
clk => output[10]~reg0.CLK
clk => output[9]~reg0.CLK
clk => output[8]~reg0.CLK
clk => output[7]~reg0.CLK
clk => output[6]~reg0.CLK
clk => output[5]~reg0.CLK
clk => output[4]~reg0.CLK
clk => output[3]~reg0.CLK
clk => output[2]~reg0.CLK
clk => output[1]~reg0.CLK
clk => output[0]~reg0.CLK
clk => output[15]~reg0.CLK
C3 => output~16.OUTPUTSELECT
C3 => output~17.OUTPUTSELECT
C3 => output~18.OUTPUTSELECT
C3 => output~19.OUTPUTSELECT
C3 => output~20.OUTPUTSELECT
C3 => output~21.OUTPUTSELECT
C3 => output~22.OUTPUTSELECT
C3 => output~23.OUTPUTSELECT
C3 => output~24.OUTPUTSELECT
C3 => output~25.OUTPUTSELECT
C3 => output~26.OUTPUTSELECT
C3 => output~27.OUTPUTSELECT
C3 => output~28.OUTPUTSELECT
C3 => output~29.OUTPUTSELECT
C3 => output~30.OUTPUTSELECT
C3 => output~31.OUTPUTSELECT
C11 => output~0.OUTPUTSELECT
C11 => output~1.OUTPUTSELECT
C11 => output~2.OUTPUTSELECT
C11 => output~3.OUTPUTSELECT
C11 => output~4.OUTPUTSELECT
C11 => output~5.OUTPUTSELECT
C11 => output~6.OUTPUTSELECT
C11 => output~7.OUTPUTSELECT
C11 => output~8.OUTPUTSELECT
C11 => output~9.OUTPUTSELECT
C11 => output~10.OUTPUTSELECT
C11 => output~11.OUTPUTSELECT
C11 => output~12.OUTPUTSELECT
C11 => output~13.OUTPUTSELECT
C11 => output~14.OUTPUTSELECT
C11 => output~15.OUTPUTSELECT
MEM_DATA[0] => output~31.DATAB
MEM_DATA[1] => output~30.DATAB
MEM_DATA[2] => output~29.DATAB
MEM_DATA[3] => output~28.DATAB
MEM_DATA[4] => output~27.DATAB
MEM_DATA[5] => output~26.DATAB
MEM_DATA[6] => output~25.DATAB
MEM_DATA[7] => output~24.DATAB
MEM_DATA[8] => output~23.DATAB
MEM_DATA[9] => output~22.DATAB
MEM_DATA[10] => output~21.DATAB
MEM_DATA[11] => output~20.DATAB
MEM_DATA[12] => output~19.DATAB
MEM_DATA[13] => output~18.DATAB
MEM_DATA[14] => output~17.DATAB
MEM_DATA[15] => output~16.DATAB
ACC_DATA[0] => output~15.DATAB
ACC_DATA[1] => output~14.DATAB
ACC_DATA[2] => output~13.DATAB
ACC_DATA[3] => output~12.DATAB
ACC_DATA[4] => output~11.DATAB
ACC_DATA[5] => output~10.DATAB
ACC_DATA[6] => output~9.DATAB
ACC_DATA[7] => output~8.DATAB
ACC_DATA[8] => output~7.DATAB
ACC_DATA[9] => output~6.DATAB
ACC_DATA[10] => output~5.DATAB
ACC_DATA[11] => output~4.DATAB
ACC_DATA[12] => output~3.DATAB
ACC_DATA[13] => output~2.DATAB
ACC_DATA[14] => output~1.DATAB
ACC_DATA[15] => output~0.DATAB
output[0] <= output[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
output[1] <= output[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
output[2] <= output[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
output[3] <= output[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
output[4] <= output[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
output[5] <= output[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
output[6] <= output[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
output[7] <= output[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
output[8] <= output[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
output[9] <= output[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
output[10] <= output[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE
output[11] <= output[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE
output[12] <= output[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE
output[13] <= output[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE
output[14] <= output[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE
output[15] <= output[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|cpu|ram:inst17
address[0] => lpm_ram_dq:lpm_ram_dq_component.address[0]
address[1] => lpm_ram_dq:lpm_ram_dq_component.address[1]
address[2] => lpm_ram_dq:lpm_ram_dq_component.address[2]
address[3] => lpm_ram_dq:lpm_ram_dq_component.address[3]
address[4] => lpm_ram_dq:lpm_ram_dq_component.address[4]
address[5] => lpm_ram_dq:lpm_ram_dq_component.address[5]
address[6] => lpm_ram_dq:lpm_ram_dq_component.address[6]
address[7] => lpm_ram_dq:lpm_ram_dq_component.address[7]
data[0] => lpm_ram_dq:lpm_ram_dq_component.data[0]
data[1] => lpm_ram_dq:lpm_ram_dq_component.data[1]
data[2] => lpm_ram_dq:lpm_ram_dq_component.data[2]
data[3] => lpm_ram_dq:lpm_ram_dq_component.data[3]
data[4] => lpm_ram_dq:lpm_ram_dq_component.data[4]
data[5] => lpm_ram_dq:lpm_ram_dq_component.data[5]
data[6] => lpm_ram_dq:lpm_ram_dq_component.data[6]
data[7] => lpm_ram_dq:lpm_ram_dq_component.data[7]
data[8] => lpm_ram_dq:lpm_ram_dq_component.data[8]
data[9] => lpm_ram_dq:lpm_ram_dq_component.data[9]
data[10] => lpm_ram_dq:lpm_ram_dq_component.data[10]
data[11] => lpm_ram_dq:lpm_ram_dq_component.data[11]
data[12] => lpm_ram_dq:lpm_ram_dq_component.data[12]
data[13] => lpm_ram_dq:lpm_ram_dq_component.data[13]
data[14] => lpm_ram_dq:lpm_ram_dq_component.data[14]
data[15] => lpm_ram_dq:lpm_ram_dq_component.data[15]
inclock => lpm_ram_dq:lpm_ram_dq_component.inclock
we => lpm_ram_dq:lpm_ram_dq_component.we
q[0] <= lpm_ram_dq:lpm_ram_dq_component.q[0]
q[1] <= lpm_ram_dq:lpm_ram_dq_component.q[1]
q[2] <= lpm_ram_dq:lpm_ram_dq_component.q[2]
q[3] <= lpm_ram_dq:lpm_ram_dq_component.q[3]
q[4] <= lpm_ram_dq:lpm_ram_dq_component.q[4]
q[5] <= lpm_ram_dq:lpm_ram_dq_component.q[5]
q[6] <= lpm_ram_dq:lpm_ram_dq_component.q[6]
q[7] <= lpm_ram_dq:lpm_ram_dq_component.q[7]
q[8] <= lpm_ram_dq:lpm_ram_dq_component.q[8]
q[9] <= lpm_ram_dq:lpm_ram_dq_component.q[9]
q[10] <= lpm_ram_dq:lpm_ram_dq_component.q[10]
q[11] <= lpm_ram_dq:lpm_ram_dq_component.q[11]
q[12] <= lpm_ram_dq:lpm_ram_dq_component.q[12]
q[13] <= lpm_ram_dq:lpm_ram_dq_component.q[13]
q[14] <= lpm_ram_dq:lpm_ram_dq_component.q[14]
q[15] <= lpm_ram_dq:lpm_ram_dq_component.q[15]


|cpu|ram:inst17|lpm_ram_dq:lpm_ram_dq_component
data[0] => altram:sram.data[0]
data[1] => altram:sram.data[1]
data[2] => altram:sram.data[2]
data[3] => altram:sram.data[3]
data[4] => altram:sram.data[4]
data[5] => altram:sram.data[5]
data[6] => altram:sram.data[6]
data[7] => altram:sram.data[7]
data[8] => altram:sram.data[8]
data[9] => altram:sram.data[9]
data[10] => altram:sram.data[10]
data[11] => altram:sram.data[11]
data[12] => altram:sram.data[12]
data[13] => altram:sram.data[13]
data[14] => altram:sram.data[14]
data[15] => altram:sram.data[15]
address[0] => altram:sram.address[0]
address[1] => altram:sram.address[1]
address[2] => altram:sram.address[2]
address[3] => altram:sram.address[3]
address[4] => altram:sram.address[4]
address[5] => altram:sram.address[5]
address[6] => altram:sram.address[6]
address[7] => altram:sram.address[7]
inclock => altram:sram.clocki
outclock => ~NO_FANOUT~
we => altram:sram.we
q[0] <= altram:sram.q[0]
q[1] <= altram:sram.q[1]
q[2] <= altram:sram.q[2]
q[3] <= altram:sram.q[3]
q[4] <= altram:sram.q[4]
q[5] <= altram:sram.q[5]
q[6] <= altram:sram.q[6]
q[7] <= altram:sram.q[7]
q[8] <= altram:sram.q[8]
q[9] <= altram:sram.q[9]
q[10] <= altram:sram.q[10]
q[11] <= altram:sram.q[11]
q[12] <= altram:sram.q[12]
q[13] <= altram:sram.q[13]
q[14] <= altram:sram.q[14]
q[15] <= altram:sram.q[15]


|cpu|ram:inst17|lpm_ram_dq:lpm_ram_dq_component|altram:sram
we => segment[0][15].WE
we => segment[0][14].WE
we => segment[0][13].WE
we => segment[0][12].WE
we => segment[0][11].WE
we => segment[0][10].WE
we => segment[0][9].WE
we => segment[0][8].WE
we => segment[0][7].WE
we => segment[0][6].WE
we => segment[0][5].WE
we => segment[0][4].WE
we => segment[0][3].WE
we => segment[0][2].WE
we => segment[0][1].WE
we => segment[0][0].WE
data[0] => segment[0][0].DATAIN
data[1] => segment[0][1].DATAIN
data[2] => segment[0][2].DATAIN
data[3] => segment[0][3].DATAIN
data[4] => segment[0][4].DATAIN
data[5] => segment[0][5].DATAIN
data[6] => segment[0][6].DATAIN
data[7] => segment[0][7].DATAIN
data[8] => segment[0][8].DATAIN
data[9] => segment[0][9].DATAIN
data[10] => segment[0][10].DATAIN
data[11] => segment[0][11].DATAIN
data[12] => segment[0][12].DATAIN
data[13] => segment[0][13].DATAIN
data[14] => segment[0][14].DATAIN
data[15] => segment[0][15].DATAIN
address[0] => segment[0][15].WADDR
address[0] => segment[0][15].RADDR
address[0] => segment[0][14].WADDR
address[0] => segment[0][14].RADDR
address[0] => segment[0][13].WADDR
address[0] => segment[0][13].RADDR
address[0] => segment[0][12].WADDR
address[0] => segment[0][12].RADDR
address[0] => segment[0][11].WADDR
address[0] => segment[0][11].RADDR
address[0] => segment[0][10].WADDR
address[0] => segment[0][10].RADDR
address[0] => segment[0][9].WADDR
address[0] => segment[0][9].RADDR
address[0] => segment[0][8].WADDR
address[0] => segment[0][8].RADDR
address[0] => segment[0][7].WADDR
address[0] => segment[0][7].RADDR
address[0] => segment[0][6].WADDR
address[0] => segment[0][6].RADDR
address[0] => segment[0][5].WADDR
address[0] => segment[0][5].RADDR
address[0] => segment[0][4].WADDR
address[0] => segment[0][4].RADDR
address[0] => segment[0][3].WADDR
address[0] => segment[0][3].RADDR
address[0] => segment[0][2].WADDR
address[0] => segment[0][2].RADDR
address[0] => segment[0][1].WADDR
address[0] => segment[0][1].RADDR
address[0] => segment[0][0].WADDR
address[0] => segment[0][0].RADDR
address[1] => segment[0][15].WADDR1
address[1] => segment[0][15].RADDR1
address[1] => segment[0][14].WADDR1
address[1] => segment[0][14].RADDR1
address[1] => segment[0][13].WADDR1
address[1] => segment[0][13].RADDR1
address[1] => segment[0][12].WADDR1
address[1] => segment[0][12].RADDR1
address[1] => segment[0][11].WADDR1
address[1] => segment[0][11].RADDR1
address[1] => segment[0][10].WADDR1
address[1] => segment[0][10].RADDR1
address[1] => segment[0][9].WADDR1
address[1] => segment[0][9].RADDR1
address[1] => segment[0][8].WADDR1
address[1] => segment[0][8].RADDR1
address[1] => segment[0][7].WADDR1
address[1] => segment[0][7].RADDR1
address[1] => segment[0][6].WADDR1
address[1] => segment[0][6].RADDR1
address[1] => segment[0][5].WADDR1
address[1] => segment[0][5].RADDR1
address[1] => segment[0][4].WADDR1
address[1] => segment[0][4].RADDR1
address[1] => segment[0][3].WADDR1
address[1] => segment[0][3].RADDR1
address[1] => segment[0][2].WADDR1
address[1] => segment[0][2].RADDR1
address[1] => segment[0][1].WADDR1
address[1] => segment[0][1].RADDR1
address[1] => segment[0][0].WADDR1
address[1] => segment[0][0].RADDR1
address[2] => segment[0][15].WADDR2
address[2] => segment[0][15].RADDR2
address[2] => segment[0][14].WADDR2
address[2] => segment[0][14].RADDR2
address[2] => segment[0][13].WADDR2
address[2] => segment[0][13].RADDR2
address[2] => segment[0][12].WADDR2
address[2] => segment[0][12].RADDR2
address[2] => segment[0][11].WADDR2
address[2] => segment[0][11].RADDR2
address[2] => segment[0][10].WADDR2
address[2] => segment[0][10].RADDR2
address[2] => segment[0][9].WADDR2
address[2] => segment[0][9].RADDR2
address[2] => segment[0][8].WADDR2
address[2] => segment[0][8].RADDR2
address[2] => segment[0][7].WADDR2
address[2] => segment[0][7].RADDR2
address[2] => segment[0][6].WADDR2
address[2] => segment[0][6].RADDR2
address[2] => segment[0][5].WADDR2
address[2] => segment[0][5].RADDR2
address[2] => segment[0][4].WADDR2
address[2] => segment[0][4].RADDR2
address[2] => segment[0][3].WADDR2
address[2] => segment[0][3].RADDR2
address[2] => segment[0][2].WADDR2
address[2] => segment[0][2].RADDR2
address[2] => segment[0][1].WADDR2
address[2] => segment[0][1].RADDR2
address[2] => segment[0][0].WADDR2
address[2] => segment[0][0].RADDR2
address[3] => segment[0][15].WADDR3
address[3] => segment[0][15].RADDR3
address[3] => segment[0][14].WADDR3
address[3] => segment[0][14].RADDR3
address[3] => segment[0][13].WADDR3
address[3] => segment[0][13].RADDR3
address[3] => segment[0][12].WADDR3
address[3] => segment[0][12].RADDR3
address[3] => segment[0][11].WADDR3
address[3] => segment[0][11].RADDR3
address[3] => segment[0][10].WADDR3
address[3] => segment[0][10].RADDR3
address[3] => segment[0][9].WADDR3
address[3] => segment[0][9].RADDR3
address[3] => segment[0][8].WADDR3
address[3] => segment[0][8].RADDR3
address[3] => segment[0][7].WADDR3
address[3] => segment[0][7].RADDR3
address[3] => segment[0][6].WADDR3
address[3] => segment[0][6].RADDR3
address[3] => segment[0][5].WADDR3
address[3] => segment[0][5].RADDR3
address[3] => segment[0][4].WADDR3
address[3] => segment[0][4].RADDR3
address[3] => segment[0][3].WADDR3
address[3] => segment[0][3].RADDR3
address[3] => segment[0][2].WADDR3
address[3] => segment[0][2].RADDR3
address[3] => segment[0][1].WADDR3
address[3] => segment[0][1].RADDR3
address[3] => segment[0][0].WADDR3
address[3] => segment[0][0].RADDR3
address[4] => segment[0][15].WADDR4
address[4] => segment[0][15].RADDR4
address[4] => segment[0][14].WADDR4
address[4] => segment[0][14].RADDR4
address[4] => segment[0][13].WADDR4
address[4] => segment[0][13].RADDR4
address[4] => segment[0][12].WADDR4
address[4] => segment[0][12].RADDR4
address[4] => segment[0][11].WADDR4
address[4] => segment[0][11].RADDR4
address[4] => segment[0][10].WADDR4
address[4] => segment[0][10].RADDR4
address[4] => segment[0][9].WADDR4
address[4] => segment[0][9].RADDR4
address[4] => segment[0][8].WADDR4
address[4] => segment[0][8].RADDR4
address[4] => segment[0][7].WADDR4
address[4] => segment[0][7].RADDR4
address[4] => segment[0][6].WADDR4
address[4] => segment[0][6].RADDR4
address[4] => segment[0][5].WADDR4
address[4] => segment[0][5].RADDR4
address[4] => segment[0][4].WADDR4
address[4] => segment[0][4].RADDR4
address[4] => segment[0][3].WADDR4
address[4] => segment[0][3].RADDR4
address[4] => segment[0][2].WADDR4
address[4] => segment[0][2].RADDR4
address[4] => segment[0][1].WADDR4
address[4] => segment[0][1].RADDR4
address[4] => segment[0][0].WADDR4
address[4] => segment[0][0].RADDR4
address[5] => segment[0][15].WADDR5
address[5] => segment[0][15].RADDR5
address[5] => segment[0][14].WADDR5
address[5] => segment[0][14].RADDR5
address[5] => segment[0][13].WADDR5
address[5] => segment[0][13].RADDR5
address[5] => segment[0][12].WADDR5
address[5] => segment[0][12].RADDR5
address[5] => seg