cpu.hier_info

来自「实现了CPU的基本功能」· HIER_INFO 代码 · 共 2,023 行 · 第 1/5 页

address[4] => segment[0][16].WADDR4
address[4] => segment[0][16].RADDR4
address[4] => segment[0][15].WADDR4
address[4] => segment[0][15].RADDR4
address[4] => segment[0][14].WADDR4
address[4] => segment[0][14].RADDR4
address[4] => segment[0][13].WADDR4
address[4] => segment[0][13].RADDR4
address[4] => segment[0][12].WADDR4
address[4] => segment[0][12].RADDR4
address[4] => segment[0][11].WADDR4
address[4] => segment[0][11].RADDR4
address[4] => segment[0][10].WADDR4
address[4] => segment[0][10].RADDR4
address[4] => segment[0][9].WADDR4
address[4] => segment[0][9].RADDR4
address[4] => segment[0][8].WADDR4
address[4] => segment[0][8].RADDR4
address[4] => segment[0][7].WADDR4
address[4] => segment[0][7].RADDR4
address[4] => segment[0][6].WADDR4
address[4] => segment[0][6].RADDR4
address[4] => segment[0][5].WADDR4
address[4] => segment[0][5].RADDR4
address[4] => segment[0][4].WADDR4
address[4] => segment[0][4].RADDR4
address[4] => segment[0][3].WADDR4
address[4] => segment[0][3].RADDR4
address[4] => segment[0][2].WADDR4
address[4] => segment[0][2].RADDR4
address[4] => segment[0][1].WADDR4
address[4] => segment[0][1].RADDR4
address[4] => segment[0][0].WADDR4
address[4] => segment[0][0].RADDR4
address[5] => segment[0][25].WADDR5
address[5] => segment[0][25].RADDR5
address[5] => segment[0][24].WADDR5
address[5] => segment[0][24].RADDR5
address[5] => segment[0][23].WADDR5
address[5] => segment[0][23].RADDR5
address[5] => segment[0][22].WADDR5
address[5] => segment[0][22].RADDR5
address[5] => segment[0][21].WADDR5
address[5] => segment[0][21].RADDR5
address[5] => segment[0][20].WADDR5
address[5] => segment[0][20].RADDR5
address[5] => segment[0][19].WADDR5
address[5] => segment[0][19].RADDR5
address[5] => segment[0][18].WADDR5
address[5] => segment[0][18].RADDR5
address[5] => segment[0][17].WADDR5
address[5] => segment[0][17].RADDR5
address[5] => segment[0][16].WADDR5
address[5] => segment[0][16].RADDR5
address[5] => segment[0][15].WADDR5
address[5] => segment[0][15].RADDR5
address[5] => segment[0][14].WADDR5
address[5] => segment[0][14].RADDR5
address[5] => segment[0][13].WADDR5
address[5] => segment[0][13].RADDR5
address[5] => segment[0][12].WADDR5
address[5] => segment[0][12].RADDR5
address[5] => segment[0][11].WADDR5
address[5] => segment[0][11].RADDR5
address[5] => segment[0][10].WADDR5
address[5] => segment[0][10].RADDR5
address[5] => segment[0][9].WADDR5
address[5] => segment[0][9].RADDR5
address[5] => segment[0][8].WADDR5
address[5] => segment[0][8].RADDR5
address[5] => segment[0][7].WADDR5
address[5] => segment[0][7].RADDR5
address[5] => segment[0][6].WADDR5
address[5] => segment[0][6].RADDR5
address[5] => segment[0][5].WADDR5
address[5] => segment[0][5].RADDR5
address[5] => segment[0][4].WADDR5
address[5] => segment[0][4].RADDR5
address[5] => segment[0][3].WADDR5
address[5] => segment[0][3].RADDR5
address[5] => segment[0][2].WADDR5
address[5] => segment[0][2].RADDR5
address[5] => segment[0][1].WADDR5
address[5] => segment[0][1].RADDR5
address[5] => segment[0][0].WADDR5
address[5] => segment[0][0].RADDR5
address[6] => segment[0][25].WADDR6
address[6] => segment[0][25].RADDR6
address[6] => segment[0][24].WADDR6
address[6] => segment[0][24].RADDR6
address[6] => segment[0][23].WADDR6
address[6] => segment[0][23].RADDR6
address[6] => segment[0][22].WADDR6
address[6] => segment[0][22].RADDR6
address[6] => segment[0][21].WADDR6
address[6] => segment[0][21].RADDR6
address[6] => segment[0][20].WADDR6
address[6] => segment[0][20].RADDR6
address[6] => segment[0][19].WADDR6
address[6] => segment[0][19].RADDR6
address[6] => segment[0][18].WADDR6
address[6] => segment[0][18].RADDR6
address[6] => segment[0][17].WADDR6
address[6] => segment[0][17].RADDR6
address[6] => segment[0][16].WADDR6
address[6] => segment[0][16].RADDR6
address[6] => segment[0][15].WADDR6
address[6] => segment[0][15].RADDR6
address[6] => segment[0][14].WADDR6
address[6] => segment[0][14].RADDR6
address[6] => segment[0][13].WADDR6
address[6] => segment[0][13].RADDR6
address[6] => segment[0][12].WADDR6
address[6] => segment[0][12].RADDR6
address[6] => segment[0][11].WADDR6
address[6] => segment[0][11].RADDR6
address[6] => segment[0][10].WADDR6
address[6] => segment[0][10].RADDR6
address[6] => segment[0][9].WADDR6
address[6] => segment[0][9].RADDR6
address[6] => segment[0][8].WADDR6
address[6] => segment[0][8].RADDR6
address[6] => segment[0][7].WADDR6
address[6] => segment[0][7].RADDR6
address[6] => segment[0][6].WADDR6
address[6] => segment[0][6].RADDR6
address[6] => segment[0][5].WADDR6
address[6] => segment[0][5].RADDR6
address[6] => segment[0][4].WADDR6
address[6] => segment[0][4].RADDR6
address[6] => segment[0][3].WADDR6
address[6] => segment[0][3].RADDR6
address[6] => segment[0][2].WADDR6
address[6] => segment[0][2].RADDR6
address[6] => segment[0][1].WADDR6
address[6] => segment[0][1].RADDR6
address[6] => segment[0][0].WADDR6
address[6] => segment[0][0].RADDR6
address[7] => segment[0][25].WADDR7
address[7] => segment[0][25].RADDR7
address[7] => segment[0][24].WADDR7
address[7] => segment[0][24].RADDR7
address[7] => segment[0][23].WADDR7
address[7] => segment[0][23].RADDR7
address[7] => segment[0][22].WADDR7
address[7] => segment[0][22].RADDR7
address[7] => segment[0][21].WADDR7
address[7] => segment[0][21].RADDR7
address[7] => segment[0][20].WADDR7
address[7] => segment[0][20].RADDR7
address[7] => segment[0][19].WADDR7
address[7] => segment[0][19].RADDR7
address[7] => segment[0][18].WADDR7
address[7] => segment[0][18].RADDR7
address[7] => segment[0][17].WADDR7
address[7] => segment[0][17].RADDR7
address[7] => segment[0][16].WADDR7
address[7] => segment[0][16].RADDR7
address[7] => segment[0][15].WADDR7
address[7] => segment[0][15].RADDR7
address[7] => segment[0][14].WADDR7
address[7] => segment[0][14].RADDR7
address[7] => segment[0][13].WADDR7
address[7] => segment[0][13].RADDR7
address[7] => segment[0][12].WADDR7
address[7] => segment[0][12].RADDR7
address[7] => segment[0][11].WADDR7
address[7] => segment[0][11].RADDR7
address[7] => segment[0][10].WADDR7
address[7] => segment[0][10].RADDR7
address[7] => segment[0][9].WADDR7
address[7] => segment[0][9].RADDR7
address[7] => segment[0][8].WADDR7
address[7] => segment[0][8].RADDR7
address[7] => segment[0][7].WADDR7
address[7] => segment[0][7].RADDR7
address[7] => segment[0][6].WADDR7
address[7] => segment[0][6].RADDR7
address[7] => segment[0][5].WADDR7
address[7] => segment[0][5].RADDR7
address[7] => segment[0][4].WADDR7
address[7] => segment[0][4].RADDR7
address[7] => segment[0][3].WADDR7
address[7] => segment[0][3].RADDR7
address[7] => segment[0][2].WADDR7
address[7] => segment[0][2].RADDR7
address[7] => segment[0][1].WADDR7
address[7] => segment[0][1].RADDR7
address[7] => segment[0][0].WADDR7
address[7] => segment[0][0].RADDR7
clocki => ~NO_FANOUT~
clocko => ~NO_FANOUT~
q[0] <= segment[0][0].DATAOUT
q[1] <= segment[0][1].DATAOUT
q[2] <= segment[0][2].DATAOUT
q[3] <= segment[0][3].DATAOUT
q[4] <= segment[0][4].DATAOUT
q[5] <= segment[0][5].DATAOUT
q[6] <= segment[0][6].DATAOUT
q[7] <= segment[0][7].DATAOUT
q[8] <= segment[0][8].DATAOUT
q[9] <= segment[0][9].DATAOUT
q[10] <= segment[0][10].DATAOUT
q[11] <= segment[0][11].DATAOUT
q[12] <= segment[0][12].DATAOUT
q[13] <= segment[0][13].DATAOUT
q[14] <= segment[0][14].DATAOUT
q[15] <= segment[0][15].DATAOUT
q[16] <= segment[0][16].DATAOUT
q[17] <= segment[0][17].DATAOUT
q[18] <= segment[0][18].DATAOUT
q[19] <= segment[0][19].DATAOUT
q[20] <= segment[0][20].DATAOUT
q[21] <= segment[0][21].DATAOUT
q[22] <= segment[0][22].DATAOUT
q[23] <= segment[0][23].DATAOUT
q[24] <= segment[0][24].DATAOUT
q[25] <= segment[0][25].DATAOUT


|cpu|sequence:inst23
reset => CAR[6]~reg0.ACLR
reset => CAR[5]~reg0.ACLR
reset => CAR[4]~reg0.ACLR
reset => CAR[3]~reg0.ACLR
reset => CAR[2]~reg0.ACLR
reset => CAR[1]~reg0.ACLR
reset => CAR[0]~reg0.ACLR
reset => CAR[7]~reg0.ACLR
clk => CAR[6]~reg0.CLK
clk => CAR[5]~reg0.CLK
clk => CAR[4]~reg0.CLK
clk => CAR[3]~reg0.CLK
clk => CAR[2]~reg0.CLK
clk => CAR[1]~reg0.CLK
clk => CAR[0]~reg0.CLK
clk => CAR[7]~reg0.CLK
FLAGS[0] => Mux~7.IN255
FLAGS[1] => CAR~2.DATAB
FLAGS[1] => CAR~10.DATAB
FLAGS[1] => CAR~3.DATAB
FLAGS[1] => CAR~12.DATAB
FLAGS[1] => CAR~6.DATAB
FLAGS[1] => CAR~14.DATAB
FLAGS[1] => CAR~15.DATAB
C24 => CAR~8.OUTPUTSELECT
C24 => CAR~9.OUTPUTSELECT
C24 => CAR~10.OUTPUTSELECT
C24 => CAR~11.OUTPUTSELECT
C24 => CAR~12.OUTPUTSELECT
C24 => CAR~13.OUTPUTSELECT
C24 => CAR~14.OUTPUTSELECT
C24 => CAR~15.OUTPUTSELECT
C25 => CAR~0.OUTPUTSELECT
C25 => CAR~1.OUTPUTSELECT
C25 => CAR~2.OUTPUTSELECT
C25 => CAR~3.OUTPUTSELECT
C25 => CAR~4.OUTPUTSELECT
C25 => CAR~5.OUTPUTSELECT
C25 => CAR~6.OUTPUTSELECT
C25 => CAR~7.OUTPUTSELECT
CBR_DATA[0] => Mux~8.IN10
CBR_DATA[0] => Mux~9.IN10
CBR_DATA[0] => Mux~10.IN10
CBR_DATA[0] => Mux~11.IN10
CBR_DATA[0] => Mux~12.IN10
CBR_DATA[0] => Mux~13.IN10
CBR_DATA[0] => Mux~14.IN10
CBR_DATA[0] => Mux~15.IN10
CBR_DATA[1] => Mux~8.IN9
CBR_DATA[1] => Mux~9.IN9
CBR_DATA[1] => Mux~10.IN9
CBR_DATA[1] => Mux~11.IN9
CBR_DATA[1] => Mux~12.IN9
CBR_DATA[1] => Mux~13.IN9
CBR_DATA[1] => Mux~14.IN9
CBR_DATA[1] => Mux~15.IN9
CBR_DATA[2] => Mux~8.IN8
CBR_DATA[2] => Mux~9.IN8
CBR_DATA[2] => Mux~10.IN8
CBR_DATA[2] => Mux~11.IN8
CBR_DATA[2] => Mux~12.IN8
CBR_DATA[2] => Mux~13.IN8
CBR_DATA[2] => Mux~14.IN8
CBR_DATA[2] => Mux~15.IN8
IR_DATA[0] => Mux~2.IN263
IR_DATA[0] => Mux~3.IN263
IR_DATA[0] => Mux~4.IN263
IR_DATA[0] => Mux~5.IN263
IR_DATA[0] => Mux~6.IN263
IR_DATA[0] => Mux~7.IN263
IR_DATA[1] => Mux~0.IN134
IR_DATA[1] => Mux~1.IN134
IR_DATA[1] => Mux~2.IN262
IR_DATA[1] => Mux~3.IN262
IR_DATA[1] => Mux~4.IN262
IR_DATA[1] => Mux~5.IN262
IR_DATA[1] => Mux~6.IN262
IR_DATA[1] => Mux~7.IN262
IR_DATA[2] => Mux~0.IN133
IR_DATA[2] => Mux~1.IN133
IR_DATA[2] => Mux~2.IN261
IR_DATA[2] => Mux~3.IN261
IR_DATA[2] => Mux~4.IN261
IR_DATA[2] => Mux~5.IN261
IR_DATA[2] => Mux~6.IN261
IR_DATA[2] => Mux~7.IN261
IR_DATA[3] => Mux~0.IN132
IR_DATA[3] => Mux~1.IN132
IR_DATA[3] => Mux~2.IN260
IR_DATA[3] => Mux~3.IN260
IR_DATA[3] => Mux~4.IN260
IR_DATA[3] => Mux~5.IN260
IR_DATA[3] => Mux~6.IN260
IR_DATA[3] => Mux~7.IN260
IR_DATA[4] => Mux~0.IN131
IR_DATA[4] => Mux~1.IN131
IR_DATA[4] => Mux~2.IN259
IR_DATA[4] => Mux~3.IN259
IR_DATA[4] => Mux~4.IN259
IR_DATA[4] => Mux~5.IN259
IR_DATA[4] => Mux~6.IN259
IR_DATA[4] => Mux~7.IN259
IR_DATA[5] => Mux~0.IN130
IR_DATA[5] => Mux~1.IN130
IR_DATA[5] => Mux~2.IN258
IR_DATA[5] => Mux~3.IN258
IR_DATA[5] => Mux~4.IN258
IR_DATA[5] => Mux~5.IN258
IR_DATA[5] => Mux~6.IN258
IR_DATA[5] => Mux~7.IN258
IR_DATA[6] => Mux~0.IN129
IR_DATA[6] => Mux~1.IN129
IR_DATA[6] => Mux~2.IN257
IR_DATA[6] => Mux~3.IN257
IR_DATA[6] => Mux~4.IN257
IR_DATA[6] => Mux~5.IN257
IR_DATA[6] => Mux~6.IN257
IR_DATA[6] => Mux~7.IN257
IR_DATA[7] => Mux~0.IN128
IR_DATA[7] => Mux~1.IN128
IR_DATA[7] => Mux~2.IN256
IR_DATA[7] => Mux~3.IN256
IR_DATA[7] => Mux~4.IN256
IR_DATA[7] => Mux~5.IN256
IR_DATA[7] => Mux~6.IN256
IR_DATA[7] => Mux~7.IN256
CAR[0] <= CAR[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
CAR[1] <= CAR[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
CAR[2] <= CAR[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
CAR[3] <= CAR[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
CAR[4] <= CAR[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
CAR[5] <= CAR[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
CAR[6] <= CAR[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
CAR[7] <= CAR[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|cpu|IR:inst22
reset => output[6]~reg0.ACLR
reset => output[5]~reg0.ACLR
reset => output[4]~reg0.ACLR
reset => output[3]~reg0.ACLR
reset => output[2]~reg0.ACLR
reset => output[1]~reg0.ACLR
reset => output[0]~reg0.ACLR
reset => output[7]~reg0.ACLR
C9 => output[6]~reg0.ENA
C9 => output[5]~reg0.ENA
C9 => output[4]~reg0.ENA
C9 => output[3]~reg0.ENA
C9 => output[2]~reg0.ENA
C9 => output[1]~reg0.ENA
C9 => output[0]~reg0.ENA
C9 => output[7]~reg0.ENA
clk => output[6]~reg0.CLK
clk => output[5]~reg0.CLK
clk => output[4]~reg0.CLK
clk => output[3]~reg0.CLK
clk => output[2]~reg0.CLK
clk => output[1]~reg0.CLK
clk => output[0]~reg0.CLK
clk => output[7]~reg0.CLK
MBR_DATA[0] => output[0]~reg0.DATAIN
MBR_DATA[1] => output[1]~reg0.DATAIN
MBR_DATA[2] => output[2]~reg0.DATAIN
MBR_DATA[3] => output[3]~reg0.DATAIN
MBR_DATA[4] => output[4]~reg0.DATAIN
MBR_DATA[5] => output[5]~reg0.DATAIN
MBR_DATA[6] => output[6]~reg0.DATAIN
MBR_DATA[7] => output[7]~reg0.DATAIN
output[0] <= output[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
output[1] <= output[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
output[2] <= output[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
output[3] <= output[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
output[4] <= output[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
output[5] <= output[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
output[6] <= output[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
output[7] <= output[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|cpu|MBR:inst18
reset => output[14]~reg0.ACLR
reset => output[13]~reg0.ACLR
reset => output[12]~reg0.ACLR
reset => output[11]~reg0.ACLR