cpu.hier_info

来自「实现了CPU的基本功能」· HIER_INFO 代码 · 共 2,023 行 · 第 1/5 页

reset => output[8]~reg0.ACLR
reset => output[7]~reg0.ACLR
reset => output[6]~reg0.ACLR
reset => output[5]~reg0.ACLR
reset => output[4]~reg0.ACLR
reset => output[3]~reg0.ACLR
reset => output[2]~reg0.ACLR
reset => output[1]~reg0.ACLR
reset => output[0]~reg0.ACLR
reset => output[15]~reg0.ACLR
clk => output[14]~reg0.CLK
clk => output[13]~reg0.CLK
clk => output[12]~reg0.CLK
clk => output[11]~reg0.CLK
clk => output[10]~reg0.CLK
clk => output[9]~reg0.CLK
clk => output[8]~reg0.CLK
clk => output[7]~reg0.CLK
clk => output[6]~reg0.CLK
clk => output[5]~reg0.CLK
clk => output[4]~reg0.CLK
clk => output[3]~reg0.CLK
clk => output[2]~reg0.CLK
clk => output[1]~reg0.CLK
clk => output[0]~reg0.CLK
clk => output[15]~reg0.CLK
C10 => output[14]~reg0.ENA
C10 => output[13]~reg0.ENA
C10 => output[12]~reg0.ENA
C10 => output[11]~reg0.ENA
C10 => output[10]~reg0.ENA
C10 => output[9]~reg0.ENA
C10 => output[8]~reg0.ENA
C10 => output[7]~reg0.ENA
C10 => output[6]~reg0.ENA
C10 => output[5]~reg0.ENA
C10 => output[4]~reg0.ENA
C10 => output[3]~reg0.ENA
C10 => output[2]~reg0.ENA
C10 => output[1]~reg0.ENA
C10 => output[0]~reg0.ENA
C10 => output[15]~reg0.ENA
MBR_DATA[0] => output[0]~reg0.DATAIN
MBR_DATA[1] => output[1]~reg0.DATAIN
MBR_DATA[2] => output[2]~reg0.DATAIN
MBR_DATA[3] => output[3]~reg0.DATAIN
MBR_DATA[4] => output[4]~reg0.DATAIN
MBR_DATA[5] => output[5]~reg0.DATAIN
MBR_DATA[6] => output[6]~reg0.DATAIN
MBR_DATA[7] => output[7]~reg0.DATAIN
MBR_DATA[8] => output[8]~reg0.DATAIN
MBR_DATA[9] => output[9]~reg0.DATAIN
MBR_DATA[10] => output[10]~reg0.DATAIN
MBR_DATA[11] => output[11]~reg0.DATAIN
MBR_DATA[12] => output[12]~reg0.DATAIN
MBR_DATA[13] => output[13]~reg0.DATAIN
MBR_DATA[14] => output[14]~reg0.DATAIN
MBR_DATA[15] => output[15]~reg0.DATAIN
output[0] <= output[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
output[1] <= output[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
output[2] <= output[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
output[3] <= output[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
output[4] <= output[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
output[5] <= output[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
output[6] <= output[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
output[7] <= output[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
output[8] <= output[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
output[9] <= output[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
output[10] <= output[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE
output[11] <= output[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE
output[12] <= output[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE
output[13] <= output[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE
output[14] <= output[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE
output[15] <= output[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|cpu|rom:inst24
address[0] => lpm_rom:lpm_rom_component.address[0]
address[1] => lpm_rom:lpm_rom_component.address[1]
address[2] => lpm_rom:lpm_rom_component.address[2]
address[3] => lpm_rom:lpm_rom_component.address[3]
address[4] => lpm_rom:lpm_rom_component.address[4]
address[5] => lpm_rom:lpm_rom_component.address[5]
address[6] => lpm_rom:lpm_rom_component.address[6]
address[7] => lpm_rom:lpm_rom_component.address[7]
q[0] <= lpm_rom:lpm_rom_component.q[0]
q[1] <= lpm_rom:lpm_rom_component.q[1]
q[2] <= lpm_rom:lpm_rom_component.q[2]
q[3] <= lpm_rom:lpm_rom_component.q[3]
q[4] <= lpm_rom:lpm_rom_component.q[4]
q[5] <= lpm_rom:lpm_rom_component.q[5]
q[6] <= lpm_rom:lpm_rom_component.q[6]
q[7] <= lpm_rom:lpm_rom_component.q[7]
q[8] <= lpm_rom:lpm_rom_component.q[8]
q[9] <= lpm_rom:lpm_rom_component.q[9]
q[10] <= lpm_rom:lpm_rom_component.q[10]
q[11] <= lpm_rom:lpm_rom_component.q[11]
q[12] <= lpm_rom:lpm_rom_component.q[12]
q[13] <= lpm_rom:lpm_rom_component.q[13]
q[14] <= lpm_rom:lpm_rom_component.q[14]
q[15] <= lpm_rom:lpm_rom_component.q[15]
q[16] <= lpm_rom:lpm_rom_component.q[16]
q[17] <= lpm_rom:lpm_rom_component.q[17]
q[18] <= lpm_rom:lpm_rom_component.q[18]
q[19] <= lpm_rom:lpm_rom_component.q[19]
q[20] <= lpm_rom:lpm_rom_component.q[20]
q[21] <= lpm_rom:lpm_rom_component.q[21]
q[22] <= lpm_rom:lpm_rom_component.q[22]
q[23] <= lpm_rom:lpm_rom_component.q[23]
q[24] <= lpm_rom:lpm_rom_component.q[24]
q[25] <= lpm_rom:lpm_rom_component.q[25]


|cpu|rom:inst24|lpm_rom:lpm_rom_component
address[0] => altrom:srom.address[0]
address[1] => altrom:srom.address[1]
address[2] => altrom:srom.address[2]
address[3] => altrom:srom.address[3]
address[4] => altrom:srom.address[4]
address[5] => altrom:srom.address[5]
address[6] => altrom:srom.address[6]
address[7] => altrom:srom.address[7]
inclock => ~NO_FANOUT~
outclock => ~NO_FANOUT~
memenab => otri[25].OE
memenab => otri[24].OE
memenab => otri[23].OE
memenab => otri[22].OE
memenab => otri[21].OE
memenab => otri[20].OE
memenab => otri[19].OE
memenab => otri[18].OE
memenab => otri[17].OE
memenab => otri[16].OE
memenab => otri[15].OE
memenab => otri[14].OE
memenab => otri[13].OE
memenab => otri[12].OE
memenab => otri[11].OE
memenab => otri[10].OE
memenab => otri[9].OE
memenab => otri[8].OE
memenab => otri[7].OE
memenab => otri[6].OE
memenab => otri[5].OE
memenab => otri[4].OE
memenab => otri[3].OE
memenab => otri[2].OE
memenab => otri[1].OE
memenab => otri[0].OE
q[0] <= otri[0].DB_MAX_OUTPUT_PORT_TYPE
q[1] <= otri[1].DB_MAX_OUTPUT_PORT_TYPE
q[2] <= otri[2].DB_MAX_OUTPUT_PORT_TYPE
q[3] <= otri[3].DB_MAX_OUTPUT_PORT_TYPE
q[4] <= otri[4].DB_MAX_OUTPUT_PORT_TYPE
q[5] <= otri[5].DB_MAX_OUTPUT_PORT_TYPE
q[6] <= otri[6].DB_MAX_OUTPUT_PORT_TYPE
q[7] <= otri[7].DB_MAX_OUTPUT_PORT_TYPE
q[8] <= otri[8].DB_MAX_OUTPUT_PORT_TYPE
q[9] <= otri[9].DB_MAX_OUTPUT_PORT_TYPE
q[10] <= otri[10].DB_MAX_OUTPUT_PORT_TYPE
q[11] <= otri[11].DB_MAX_OUTPUT_PORT_TYPE
q[12] <= otri[12].DB_MAX_OUTPUT_PORT_TYPE
q[13] <= otri[13].DB_MAX_OUTPUT_PORT_TYPE
q[14] <= otri[14].DB_MAX_OUTPUT_PORT_TYPE
q[15] <= otri[15].DB_MAX_OUTPUT_PORT_TYPE
q[16] <= otri[16].DB_MAX_OUTPUT_PORT_TYPE
q[17] <= otri[17].DB_MAX_OUTPUT_PORT_TYPE
q[18] <= otri[18].DB_MAX_OUTPUT_PORT_TYPE
q[19] <= otri[19].DB_MAX_OUTPUT_PORT_TYPE
q[20] <= otri[20].DB_MAX_OUTPUT_PORT_TYPE
q[21] <= otri[21].DB_MAX_OUTPUT_PORT_TYPE
q[22] <= otri[22].DB_MAX_OUTPUT_PORT_TYPE
q[23] <= otri[23].DB_MAX_OUTPUT_PORT_TYPE
q[24] <= otri[24].DB_MAX_OUTPUT_PORT_TYPE
q[25] <= otri[25].DB_MAX_OUTPUT_PORT_TYPE


|cpu|rom:inst24|lpm_rom:lpm_rom_component|altrom:srom
address[0] => segment[0][25].WADDR
address[0] => segment[0][25].RADDR
address[0] => segment[0][24].WADDR
address[0] => segment[0][24].RADDR
address[0] => segment[0][23].WADDR
address[0] => segment[0][23].RADDR
address[0] => segment[0][22].WADDR
address[0] => segment[0][22].RADDR
address[0] => segment[0][21].WADDR
address[0] => segment[0][21].RADDR
address[0] => segment[0][20].WADDR
address[0] => segment[0][20].RADDR
address[0] => segment[0][19].WADDR
address[0] => segment[0][19].RADDR
address[0] => segment[0][18].WADDR
address[0] => segment[0][18].RADDR
address[0] => segment[0][17].WADDR
address[0] => segment[0][17].RADDR
address[0] => segment[0][16].WADDR
address[0] => segment[0][16].RADDR
address[0] => segment[0][15].WADDR
address[0] => segment[0][15].RADDR
address[0] => segment[0][14].WADDR
address[0] => segment[0][14].RADDR
address[0] => segment[0][13].WADDR
address[0] => segment[0][13].RADDR
address[0] => segment[0][12].WADDR
address[0] => segment[0][12].RADDR
address[0] => segment[0][11].WADDR
address[0] => segment[0][11].RADDR
address[0] => segment[0][10].WADDR
address[0] => segment[0][10].RADDR
address[0] => segment[0][9].WADDR
address[0] => segment[0][9].RADDR
address[0] => segment[0][8].WADDR
address[0] => segment[0][8].RADDR
address[0] => segment[0][7].WADDR
address[0] => segment[0][7].RADDR
address[0] => segment[0][6].WADDR
address[0] => segment[0][6].RADDR
address[0] => segment[0][5].WADDR
address[0] => segment[0][5].RADDR
address[0] => segment[0][4].WADDR
address[0] => segment[0][4].RADDR
address[0] => segment[0][3].WADDR
address[0] => segment[0][3].RADDR
address[0] => segment[0][2].WADDR
address[0] => segment[0][2].RADDR
address[0] => segment[0][1].WADDR
address[0] => segment[0][1].RADDR
address[0] => segment[0][0].WADDR
address[0] => segment[0][0].RADDR
address[1] => segment[0][25].WADDR1
address[1] => segment[0][25].RADDR1
address[1] => segment[0][24].WADDR1
address[1] => segment[0][24].RADDR1
address[1] => segment[0][23].WADDR1
address[1] => segment[0][23].RADDR1
address[1] => segment[0][22].WADDR1
address[1] => segment[0][22].RADDR1
address[1] => segment[0][21].WADDR1
address[1] => segment[0][21].RADDR1
address[1] => segment[0][20].WADDR1
address[1] => segment[0][20].RADDR1
address[1] => segment[0][19].WADDR1
address[1] => segment[0][19].RADDR1
address[1] => segment[0][18].WADDR1
address[1] => segment[0][18].RADDR1
address[1] => segment[0][17].WADDR1
address[1] => segment[0][17].RADDR1
address[1] => segment[0][16].WADDR1
address[1] => segment[0][16].RADDR1
address[1] => segment[0][15].WADDR1
address[1] => segment[0][15].RADDR1
address[1] => segment[0][14].WADDR1
address[1] => segment[0][14].RADDR1
address[1] => segment[0][13].WADDR1
address[1] => segment[0][13].RADDR1
address[1] => segment[0][12].WADDR1
address[1] => segment[0][12].RADDR1
address[1] => segment[0][11].WADDR1
address[1] => segment[0][11].RADDR1
address[1] => segment[0][10].WADDR1
address[1] => segment[0][10].RADDR1
address[1] => segment[0][9].WADDR1
address[1] => segment[0][9].RADDR1
address[1] => segment[0][8].WADDR1
address[1] => segment[0][8].RADDR1
address[1] => segment[0][7].WADDR1
address[1] => segment[0][7].RADDR1
address[1] => segment[0][6].WADDR1
address[1] => segment[0][6].RADDR1
address[1] => segment[0][5].WADDR1
address[1] => segment[0][5].RADDR1
address[1] => segment[0][4].WADDR1
address[1] => segment[0][4].RADDR1
address[1] => segment[0][3].WADDR1
address[1] => segment[0][3].RADDR1
address[1] => segment[0][2].WADDR1
address[1] => segment[0][2].RADDR1
address[1] => segment[0][1].WADDR1
address[1] => segment[0][1].RADDR1
address[1] => segment[0][0].WADDR1
address[1] => segment[0][0].RADDR1
address[2] => segment[0][25].WADDR2
address[2] => segment[0][25].RADDR2
address[2] => segment[0][24].WADDR2
address[2] => segment[0][24].RADDR2
address[2] => segment[0][23].WADDR2
address[2] => segment[0][23].RADDR2
address[2] => segment[0][22].WADDR2
address[2] => segment[0][22].RADDR2
address[2] => segment[0][21].WADDR2
address[2] => segment[0][21].RADDR2
address[2] => segment[0][20].WADDR2
address[2] => segment[0][20].RADDR2
address[2] => segment[0][19].WADDR2
address[2] => segment[0][19].RADDR2
address[2] => segment[0][18].WADDR2
address[2] => segment[0][18].RADDR2
address[2] => segment[0][17].WADDR2
address[2] => segment[0][17].RADDR2
address[2] => segment[0][16].WADDR2
address[2] => segment[0][16].RADDR2
address[2] => segment[0][15].WADDR2
address[2] => segment[0][15].RADDR2
address[2] => segment[0][14].WADDR2
address[2] => segment[0][14].RADDR2
address[2] => segment[0][13].WADDR2
address[2] => segment[0][13].RADDR2
address[2] => segment[0][12].WADDR2
address[2] => segment[0][12].RADDR2
address[2] => segment[0][11].WADDR2
address[2] => segment[0][11].RADDR2
address[2] => segment[0][10].WADDR2
address[2] => segment[0][10].RADDR2
address[2] => segment[0][9].WADDR2
address[2] => segment[0][9].RADDR2
address[2] => segment[0][8].WADDR2
address[2] => segment[0][8].RADDR2
address[2] => segment[0][7].WADDR2
address[2] => segment[0][7].RADDR2
address[2] => segment[0][6].WADDR2
address[2] => segment[0][6].RADDR2
address[2] => segment[0][5].WADDR2
address[2] => segment[0][5].RADDR2
address[2] => segment[0][4].WADDR2
address[2] => segment[0][4].RADDR2
address[2] => segment[0][3].WADDR2
address[2] => segment[0][3].RADDR2
address[2] => segment[0][2].WADDR2
address[2] => segment[0][2].RADDR2
address[2] => segment[0][1].WADDR2
address[2] => segment[0][1].RADDR2
address[2] => segment[0][0].WADDR2
address[2] => segment[0][0].RADDR2
address[3] => segment[0][25].WADDR3
address[3] => segment[0][25].RADDR3
address[3] => segment[0][24].WADDR3
address[3] => segment[0][24].RADDR3
address[3] => segment[0][23].WADDR3
address[3] => segment[0][23].RADDR3
address[3] => segment[0][22].WADDR3
address[3] => segment[0][22].RADDR3
address[3] => segment[0][21].WADDR3
address[3] => segment[0][21].RADDR3
address[3] => segment[0][20].WADDR3
address[3] => segment[0][20].RADDR3
address[3] => segment[0][19].WADDR3
address[3] => segment[0][19].RADDR3
address[3] => segment[0][18].WADDR3
address[3] => segment[0][18].RADDR3
address[3] => segment[0][17].WADDR3
address[3] => segment[0][17].RADDR3
address[3] => segment[0][16].WADDR3
address[3] => segment[0][16].RADDR3
address[3] => segment[0][15].WADDR3
address[3] => segment[0][15].RADDR3
address[3] => segment[0][14].WADDR3
address[3] => segment[0][14].RADDR3
address[3] => segment[0][13].WADDR3
address[3] => segment[0][13].RADDR3
address[3] => segment[0][12].WADDR3
address[3] => segment[0][12].RADDR3
address[3] => segment[0][11].WADDR3
address[3] => segment[0][11].RADDR3
address[3] => segment[0][10].WADDR3
address[3] => segment[0][10].RADDR3
address[3] => segment[0][9].WADDR3
address[3] => segment[0][9].RADDR3
address[3] => segment[0][8].WADDR3
address[3] => segment[0][8].RADDR3
address[3] => segment[0][7].WADDR3
address[3] => segment[0][7].RADDR3
address[3] => segment[0][6].WADDR3
address[3] => segment[0][6].RADDR3
address[3] => segment[0][5].WADDR3
address[3] => segment[0][5].RADDR3
address[3] => segment[0][4].WADDR3
address[3] => segment[0][4].RADDR3
address[3] => segment[0][3].WADDR3
address[3] => segment[0][3].RADDR3
address[3] => segment[0][2].WADDR3
address[3] => segment[0][2].RADDR3
address[3] => segment[0][1].WADDR3
address[3] => segment[0][1].RADDR3
address[3] => segment[0][0].WADDR3
address[3] => segment[0][0].RADDR3
address[4] => segment[0][25].WADDR4
address[4] => segment[0][25].RADDR4
address[4] => segment[0][24].WADDR4
address[4] => segment[0][24].RADDR4
address[4] => segment[0][23].WADDR4
address[4] => segment[0][23].RADDR4
address[4] => segment[0][22].WADDR4
address[4] => segment[0][22].RADDR4
address[4] => segment[0][21].WADDR4
address[4] => segment[0][21].RADDR4
address[4] => segment[0][20].WADDR4
address[4] => segment[0][20].RADDR4
address[4] => segment[0][19].WADDR4
address[4] => segment[0][19].RADDR4
address[4] => segment[0][18].WADDR4
address[4] => segment[0][18].RADDR4
address[4] => segment[0][17].WADDR4
address[4] => segment[0][17].RADDR4