cpu.hier_info

来自「实现了CPU的基本功能」· HIER_INFO 代码 · 共 2,023 行 · 第 1/5 页

|cpu
ACC[0] <= ALU:inst.ACC[0]
ACC[1] <= ALU:inst.ACC[1]
ACC[2] <= ALU:inst.ACC[2]
ACC[3] <= ALU:inst.ACC[3]
ACC[4] <= ALU:inst.ACC[4]
ACC[5] <= ALU:inst.ACC[5]
ACC[6] <= ALU:inst.ACC[6]
ACC[7] <= ALU:inst.ACC[7]
ACC[8] <= ALU:inst.ACC[8]
ACC[9] <= ALU:inst.ACC[9]
ACC[10] <= ALU:inst.ACC[10]
ACC[11] <= ALU:inst.ACC[11]
ACC[12] <= ALU:inst.ACC[12]
ACC[13] <= ALU:inst.ACC[13]
ACC[14] <= ALU:inst.ACC[14]
ACC[15] <= ALU:inst.ACC[15]
RESET => ALU:inst.reset
RESET => BR:inst21.reset
RESET => sequence:inst23.reset
RESET => IR:inst22.reset
RESET => MBR:inst18.reset
RESET => MAR:inst19.reset
RESET => PC:inst20.reset
CLOCK => ALU:inst.clk
CLOCK => BR:inst21.clk
CLOCK => sequence:inst23.clk
CLOCK => IR:inst22.clk
CLOCK => MBR:inst18.clk
CLOCK => ram:inst17.inclock
CLOCK => MAR:inst19.clk
CLOCK => PC:inst20.clk
C[0] <= rom:inst24.q[0]
C[1] <= rom:inst24.q[1]
C[2] <= rom:inst24.q[2]
C[3] <= rom:inst24.q[3]
C[4] <= rom:inst24.q[4]
C[5] <= rom:inst24.q[5]
C[6] <= rom:inst24.q[6]
C[7] <= rom:inst24.q[7]
C[8] <= rom:inst24.q[8]
C[9] <= rom:inst24.q[9]
C[10] <= rom:inst24.q[10]
C[11] <= rom:inst24.q[11]
C[12] <= rom:inst24.q[12]
C[13] <= rom:inst24.q[13]
C[14] <= rom:inst24.q[14]
C[15] <= rom:inst24.q[15]
C[16] <= rom:inst24.q[16]
C[17] <= rom:inst24.q[17]
C[18] <= rom:inst24.q[18]
C[19] <= rom:inst24.q[19]
C[20] <= rom:inst24.q[20]
C[21] <= rom:inst24.q[21]
C[22] <= rom:inst24.q[22]
C[23] <= rom:inst24.q[23]
C[24] <= rom:inst24.q[24]
C[25] <= rom:inst24.q[25]
CAR[0] <= sequence:inst23.CAR[0]
CAR[1] <= sequence:inst23.CAR[1]
CAR[2] <= sequence:inst23.CAR[2]
CAR[3] <= sequence:inst23.CAR[3]
CAR[4] <= sequence:inst23.CAR[4]
CAR[5] <= sequence:inst23.CAR[5]
CAR[6] <= sequence:inst23.CAR[6]
CAR[7] <= sequence:inst23.CAR[7]
FLAGS[0] <= ALU:inst.FLAGS[0]
FLAGS[1] <= ALU:inst.FLAGS[1]
MBR[0] <= MBR:inst18.output[0]
MBR[1] <= MBR:inst18.output[1]
MBR[2] <= MBR:inst18.output[2]
MBR[3] <= MBR:inst18.output[3]
MBR[4] <= MBR:inst18.output[4]
MBR[5] <= MBR:inst18.output[5]
MBR[6] <= MBR:inst18.output[6]
MBR[7] <= MBR:inst18.output[7]
MBR[8] <= MBR:inst18.output[8]
MBR[9] <= MBR:inst18.output[9]
MBR[10] <= MBR:inst18.output[10]
MBR[11] <= MBR:inst18.output[11]
MBR[12] <= MBR:inst18.output[12]
MBR[13] <= MBR:inst18.output[13]
MBR[14] <= MBR:inst18.output[14]
MBR[15] <= MBR:inst18.output[15]
MAR[0] <= MAR:inst19.output[0]
MAR[1] <= MAR:inst19.output[1]
MAR[2] <= MAR:inst19.output[2]
MAR[3] <= MAR:inst19.output[3]
MAR[4] <= MAR:inst19.output[4]
MAR[5] <= MAR:inst19.output[5]
MAR[6] <= MAR:inst19.output[6]
MAR[7] <= MAR:inst19.output[7]
PC[0] <= PC:inst20.output[0]
PC[1] <= PC:inst20.output[1]
PC[2] <= PC:inst20.output[2]
PC[3] <= PC:inst20.output[3]
PC[4] <= PC:inst20.output[4]
PC[5] <= PC:inst20.output[5]
PC[6] <= PC:inst20.output[6]
PC[7] <= PC:inst20.output[7]
BR[0] <= BR:inst21.output[0]
BR[1] <= BR:inst21.output[1]
BR[2] <= BR:inst21.output[2]
BR[3] <= BR:inst21.output[3]
BR[4] <= BR:inst21.output[4]
BR[5] <= BR:inst21.output[5]
BR[6] <= BR:inst21.output[6]
BR[7] <= BR:inst21.output[7]
BR[8] <= BR:inst21.output[8]
BR[9] <= BR:inst21.output[9]
BR[10] <= BR:inst21.output[10]
BR[11] <= BR:inst21.output[11]
BR[12] <= BR:inst21.output[12]
BR[13] <= BR:inst21.output[13]
BR[14] <= BR:inst21.output[14]
BR[15] <= BR:inst21.output[15]
DR[0] <= ALU:inst.DR[0]
DR[1] <= ALU:inst.DR[1]
DR[2] <= ALU:inst.DR[2]
DR[3] <= ALU:inst.DR[3]
DR[4] <= ALU:inst.DR[4]
DR[5] <= ALU:inst.DR[5]
DR[6] <= ALU:inst.DR[6]
DR[7] <= ALU:inst.DR[7]
DR[8] <= ALU:inst.DR[8]
DR[9] <= ALU:inst.DR[9]
DR[10] <= ALU:inst.DR[10]
DR[11] <= ALU:inst.DR[11]
DR[12] <= ALU:inst.DR[12]
DR[13] <= ALU:inst.DR[13]
DR[14] <= ALU:inst.DR[14]
DR[15] <= ALU:inst.DR[15]
MR[0] <= ALU:inst.MR[0]
MR[1] <= ALU:inst.MR[1]
MR[2] <= ALU:inst.MR[2]
MR[3] <= ALU:inst.MR[3]
MR[4] <= ALU:inst.MR[4]
MR[5] <= ALU:inst.MR[5]
MR[6] <= ALU:inst.MR[6]
MR[7] <= ALU:inst.MR[7]
MR[8] <= ALU:inst.MR[8]
MR[9] <= ALU:inst.MR[9]
MR[10] <= ALU:inst.MR[10]
MR[11] <= ALU:inst.MR[11]
MR[12] <= ALU:inst.MR[12]
MR[13] <= ALU:inst.MR[13]
MR[14] <= ALU:inst.MR[14]
MR[15] <= ALU:inst.MR[15]


|cpu|ALU:inst
reset => temp_acc[14].ACLR
reset => temp_acc[13].ACLR
reset => temp_acc[12].ACLR
reset => temp_acc[11].ACLR
reset => temp_acc[10].ACLR
reset => temp_acc[9].ACLR
reset => temp_acc[8].ACLR
reset => temp_acc[7].ACLR
reset => temp_acc[6].ACLR
reset => temp_acc[5].ACLR
reset => temp_acc[4].ACLR
reset => temp_acc[3].ACLR
reset => temp_acc[2].ACLR
reset => temp_acc[1].ACLR
reset => temp_acc[0].ACLR
reset => FLAGS[1]~reg0.ACLR
reset => FLAGS[0]~reg0.ACLR
reset => temp_acc[15].ACLR
reset => counter[31].ENA
reset => counter[30].ENA
reset => counter[29].ENA
reset => counter[28].ENA
reset => counter[27].ENA
reset => counter[26].ENA
reset => counter[25].ENA
reset => counter[24].ENA
reset => counter[23].ENA
reset => counter[22].ENA
reset => counter[21].ENA
reset => counter[20].ENA
reset => counter[19].ENA
reset => counter[18].ENA
reset => counter[17].ENA
reset => counter[16].ENA
reset => counter[15].ENA
reset => counter[14].ENA
reset => counter[13].ENA
reset => counter[12].ENA
reset => counter[11].ENA
reset => counter[10].ENA
reset => counter[9].ENA
reset => counter[8].ENA
reset => counter[7].ENA
reset => counter[6].ENA
reset => counter[5].ENA
reset => counter[4].ENA
reset => counter[3].ENA
reset => counter[2].ENA
reset => counter[1].ENA
reset => counter[0].ENA
reset => temp_mr[16].ENA
reset => temp_mr[15].ENA
reset => temp_mr[14].ENA
reset => temp_mr[13].ENA
reset => temp_mr[12].ENA
reset => temp_mr[11].ENA
reset => temp_mr[10].ENA
reset => temp_mr[9].ENA
reset => temp_mr[8].ENA
reset => temp_mr[7].ENA
reset => temp_mr[6].ENA
reset => temp_mr[5].ENA
reset => temp_mr[4].ENA
reset => temp_mr[3].ENA
reset => temp_mr[2].ENA
reset => temp_mr[1].ENA
reset => temp_mr[0].ENA
reset => temp_dr[15].ENA
reset => temp_dr[14].ENA
reset => temp_dr[13].ENA
reset => temp_dr[12].ENA
reset => temp_dr[11].ENA
reset => temp_dr[10].ENA
reset => temp_dr[9].ENA
reset => temp_dr[8].ENA
reset => temp_dr[7].ENA
reset => temp_dr[6].ENA
reset => temp_dr[5].ENA
reset => temp_dr[4].ENA
reset => temp_dr[3].ENA
reset => temp_dr[2].ENA
reset => temp_dr[1].ENA
reset => temp_dr[0].ENA
clk => temp_acc[14].CLK
clk => temp_acc[13].CLK
clk => temp_acc[12].CLK
clk => temp_acc[11].CLK
clk => temp_acc[10].CLK
clk => temp_acc[9].CLK
clk => temp_acc[8].CLK
clk => temp_acc[7].CLK
clk => temp_acc[6].CLK
clk => temp_acc[5].CLK
clk => temp_acc[4].CLK
clk => temp_acc[3].CLK
clk => temp_acc[2].CLK
clk => temp_acc[1].CLK
clk => temp_acc[0].CLK
clk => FLAGS[1]~reg0.CLK
clk => FLAGS[0]~reg0.CLK
clk => counter[31].CLK
clk => counter[30].CLK
clk => counter[29].CLK
clk => counter[28].CLK
clk => counter[27].CLK
clk => counter[26].CLK
clk => counter[25].CLK
clk => counter[24].CLK
clk => counter[23].CLK
clk => counter[22].CLK
clk => counter[21].CLK
clk => counter[20].CLK
clk => counter[19].CLK
clk => counter[18].CLK
clk => counter[17].CLK
clk => counter[16].CLK
clk => counter[15].CLK
clk => counter[14].CLK
clk => counter[13].CLK
clk => counter[12].CLK
clk => counter[11].CLK
clk => counter[10].CLK
clk => counter[9].CLK
clk => counter[8].CLK
clk => counter[7].CLK
clk => counter[6].CLK
clk => counter[5].CLK
clk => counter[4].CLK
clk => counter[3].CLK
clk => counter[2].CLK
clk => counter[1].CLK
clk => counter[0].CLK
clk => temp_mr[16].CLK
clk => temp_mr[15].CLK
clk => temp_mr[14].CLK
clk => temp_mr[13].CLK
clk => temp_mr[12].CLK
clk => temp_mr[11].CLK
clk => temp_mr[10].CLK
clk => temp_mr[9].CLK
clk => temp_mr[8].CLK
clk => temp_mr[7].CLK
clk => temp_mr[6].CLK
clk => temp_mr[5].CLK
clk => temp_mr[4].CLK
clk => temp_mr[3].CLK
clk => temp_mr[2].CLK
clk => temp_mr[1].CLK
clk => temp_mr[0].CLK
clk => temp_dr[15].CLK
clk => temp_dr[14].CLK
clk => temp_dr[13].CLK
clk => temp_dr[12].CLK
clk => temp_dr[11].CLK
clk => temp_dr[10].CLK
clk => temp_dr[9].CLK
clk => temp_dr[8].CLK
clk => temp_dr[7].CLK
clk => temp_dr[6].CLK
clk => temp_dr[5].CLK
clk => temp_dr[4].CLK
clk => temp_dr[3].CLK
clk => temp_dr[2].CLK
clk => temp_dr[1].CLK
clk => temp_dr[0].CLK
clk => sign.CLK
clk => temp_acc[15].CLK
BR_DATA[0] => add~0.IN16
BR_DATA[0] => temp_acc~0.IN0
BR_DATA[0] => temp_acc~16.IN0
BR_DATA[0] => add~3.IN16
BR_DATA[0] => add~6.IN16
BR_DATA[0] => add~1.IN16
BR_DATA[0] => add~2.IN16
BR_DATA[0] => add~5.IN16
BR_DATA[1] => add~0.IN15
BR_DATA[1] => temp_acc~1.IN0
BR_DATA[1] => temp_acc~17.IN0
BR_DATA[1] => add~3.IN15
BR_DATA[1] => add~6.IN15
BR_DATA[1] => add~1.IN15
BR_DATA[1] => add~2.IN15
BR_DATA[1] => add~5.IN15
BR_DATA[2] => add~0.IN14
BR_DATA[2] => temp_acc~2.IN0
BR_DATA[2] => temp_acc~18.IN0
BR_DATA[2] => add~3.IN14
BR_DATA[2] => add~6.IN14
BR_DATA[2] => add~1.IN14
BR_DATA[2] => add~2.IN14
BR_DATA[2] => add~5.IN14
BR_DATA[3] => add~0.IN13
BR_DATA[3] => temp_acc~3.IN0
BR_DATA[3] => temp_acc~19.IN0
BR_DATA[3] => add~3.IN13
BR_DATA[3] => add~6.IN13
BR_DATA[3] => add~1.IN13
BR_DATA[3] => add~2.IN13
BR_DATA[3] => add~5.IN13
BR_DATA[4] => add~0.IN12
BR_DATA[4] => temp_acc~4.IN0
BR_DATA[4] => temp_acc~20.IN0
BR_DATA[4] => add~3.IN12
BR_DATA[4] => add~6.IN12
BR_DATA[4] => add~1.IN12
BR_DATA[4] => add~2.IN12
BR_DATA[4] => add~5.IN12
BR_DATA[5] => add~0.IN11
BR_DATA[5] => temp_acc~5.IN0
BR_DATA[5] => temp_acc~21.IN0
BR_DATA[5] => add~3.IN11
BR_DATA[5] => add~6.IN11
BR_DATA[5] => add~1.IN11
BR_DATA[5] => add~2.IN11
BR_DATA[5] => add~5.IN11
BR_DATA[6] => add~0.IN10
BR_DATA[6] => temp_acc~6.IN0
BR_DATA[6] => temp_acc~22.IN0
BR_DATA[6] => add~3.IN10
BR_DATA[6] => add~6.IN10
BR_DATA[6] => add~1.IN10
BR_DATA[6] => add~2.IN10
BR_DATA[6] => add~5.IN10
BR_DATA[7] => add~0.IN9
BR_DATA[7] => temp_acc~7.IN0
BR_DATA[7] => temp_acc~23.IN0
BR_DATA[7] => add~3.IN9
BR_DATA[7] => add~6.IN9
BR_DATA[7] => add~1.IN9
BR_DATA[7] => add~2.IN9
BR_DATA[7] => add~5.IN9
BR_DATA[8] => add~0.IN8
BR_DATA[8] => temp_acc~8.IN0
BR_DATA[8] => temp_acc~24.IN0
BR_DATA[8] => add~3.IN8
BR_DATA[8] => add~6.IN8
BR_DATA[8] => add~1.IN8
BR_DATA[8] => add~2.IN8
BR_DATA[8] => add~5.IN8
BR_DATA[9] => add~0.IN7
BR_DATA[9] => temp_acc~9.IN0
BR_DATA[9] => temp_acc~25.IN0
BR_DATA[9] => add~3.IN7
BR_DATA[9] => add~6.IN7
BR_DATA[9] => add~1.IN7
BR_DATA[9] => add~2.IN7
BR_DATA[9] => add~5.IN7
BR_DATA[10] => add~0.IN6
BR_DATA[10] => temp_acc~10.IN0
BR_DATA[10] => temp_acc~26.IN0
BR_DATA[10] => add~3.IN6
BR_DATA[10] => add~6.IN6
BR_DATA[10] => add~1.IN6
BR_DATA[10] => add~2.IN6