ir.vhd

来自「实现了CPU的基本功能」· VHDL 代码 · 共 22 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity IR is 
port(reset,C9,clk:in std_logic;
     MBR_DATA:in std_logic_vector(7 downto 0);
     output:out std_logic_vector(7 downto 0)
);
end entity;
architecture IR_arc of IR is
begin 
process(reset,clk,C9)
begin
if reset='1' then
   output<="00000000";
  elsif clk'event and clk='1' then
      if C9='1' then
          output<=MBR_DATA;
      end if;
end if;
end process;
end IR_arc;