br.vhd

来自「实现了CPU的基本功能」· VHDL 代码 · 共 22 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity BR is
port(reset,clk,C10:in std_logic;
     MBR_DATA:in std_logic_vector(15 downto 0);
     output:out std_logic_vector(15 downto 0)
);
end entity;
architecture BR_arc of BR is 
begin
process(reset,clk,C10)
begin
if reset='1' then
     output<="0000000000000000";
   elsif clk'event and clk='1' then
      if C10='1' then
           output<=MBR_DATA;
      end if;
end if;
end process;
end BR_arc;