mar.vhd

来自「实现了CPU的基本功能」· VHDL 代码 · 共 24 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity MAR is 
port(reset,clk,C5,C8:in std_logic;
     MBR_DATA,PC_DATA:in std_logic_vector(7 downto 0);
     output:out std_logic_vector(7 downto 0)
);
end entity;
architecture MAR_arc of MAR is 
begin
process(reset,clk,C5,C8)
begin
if reset='1' then
     output<="00000000";
   elsif clk'event and clk='1' then
        if C5='1' then
             output<=MBR_DATA;
            elsif C8='1' then
                output<=PC_DATA;
        end if;
end if;
end process;
end MAR_arc;