📄 mbr.vhd
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity MBR is
port(reset,clk,C3,C11:in std_logic;
MEM_DATA,ACC_DATA:in std_logic_vector(15 downto 0);
output:out std_logic_vector(15 downto 0)
);
end entity;
architecture MBR_arc of MBR is
begin
process(reset,clk,C3,C11)
begin
if reset='1' then
output<="0000000000000000";
elsif clk'event and clk='1' then
if C3='1' then
output<=MEM_DATA;
elsif C11='1' then
output<=ACC_DATA;
end if;
end if;
end process;
end MBR_arc;
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