📄 alu.vhd
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity ALU is
port(reset,clk:in std_logic;
BR_DATA,ACC_DATA:in std_logic_vector(15 downto 0);
CBR_DATA:in std_logic_vector(11 downto 0);
ACC,MR,DR:out std_logic_vector(15 downto 0);
FLAGS:out std_logic_vector(1 downto 0)
);
end entity;
architecture ALU_arc of ALU is
begin
process(reset,clk,CBR_DATA)
variable temp_acc:std_logic_vector(15 downto 0);
variable temp_mr:std_logic_vector(16 downto 0);
variable counter:integer;
variable sign:std_logic;
variable temp,temp_dr:std_logic_vector(15 downto 0);
begin
if reset='1' then
temp_acc:="0000000000000000";
FLAGS<="00";
elsif clk'event and clk='1' then
case CBR_DATA is
when "000000000001"=>temp_acc:="0000000000000000";
when "000000000010"=>temp_acc:=ACC_DATA+BR_DATA;
when "000000000100"=>temp_acc:=ACC_DATA-BR_DATA;
when "000000001000"=>temp_acc:=ACC_DATA and BR_DATA;
when "000000010000"=>temp_acc:=ACC_DATA or BR_DATA;
when "000000100000"=>temp_acc:=not ACC_DATA;
when "000001000000"=>temp_acc:='0'&ACC_DATA(15 downto 1);
when "000010000000"=>temp_acc:=ACC_DATA(14 downto 0)&'0';
when "000100000000"=>
counter:=16;
temp_mr:=ACC_DATA&'0';
temp_acc:="0000000000000000";
when "001000000000"=>
if temp_mr(1)='1' and temp_mr(0)='0' then
temp_acc:=temp_acc-BR_DATA;
elsif temp_mr(1)='0' and temp_mr(0)='1' then
temp_acc:=temp_acc+BR_DATA;
end if;
counter:=counter-1;
temp_mr:=temp_acc(0)&temp_mr(16 downto 1);
if temp_acc(15)='1' then
temp_acc:='1'&temp_acc(15 downto 1);
else
temp_acc:='0'&temp_acc(15 downto 1);
end if;
when "010000000000"=>
counter:=16;
temp_dr:=ACC_DATA;
if ACC_DATA(15)='1' then
temp_acc:="1111111111111111";
else
temp_acc:="0000000000000000";
end if;
if ACC_DATA(15)=BR_DATA(15) then
sign:='0';
else
sign:='1';
end if;
when "100000000000"=>
counter:=counter-1;
temp_acc:=temp_acc(14 downto 0)&temp_dr(15);
temp_dr:=temp_dr(14 downto 0)&'0';
temp:=temp_acc;
if BR_DATA(15)=temp(15) then
temp:=temp-BR_DATA;
else
temp:=temp+BR_DATA;
end if;
if temp(15)=temp_acc(15) or (temp="0000000000000000" and temp_dr="0000000000000000") then
temp_acc:=temp;
temp_dr(0):='1';
else
temp_dr(0):='0';
end if;
if counter=0 then
if sign='1' then
temp_dr:=not temp_dr;
temp_dr:=temp_dr+1;
end if;
end if;
when others=>null;
end case;
if counter=0 then
FLAGS(1)<='1';
else
FLAGS(1)<='0';
end if;
if temp_acc(15)='0' then
FLAGS(0)<='1';
else
FLAGS(0)<='0';
end if;
end if;
ACC<=temp_acc;
MR<=temp_mr(16 downto 1);
DR<=temp_dr;
end process;
end ALU_arc;
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