pc.vhd

来自「实现了CPU的基本功能」· VHDL 代码 · 共 24 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity PC is 
port(reset,clk,C6,C7:in std_logic;
     MBR_DATA:in std_logic_vector(7 downto 0);
     output:buffer std_logic_vector(7 downto 0)
);
end entity;
architecture PC_arc of PC is
begin
process(reset,clk,C6,C7)
begin 
if reset='1' then
     output<="00000000";
   elsif clk'event and clk='1' then 
       if C6='1' then
           output<=MBR_DATA;
         elsif C7='1' then
            output<=output+1;
       end if;
end if;
end process;
end PC_arc;